Z86L70 Datasheet, PDF (42/61 Pages) Zilog, Inc. – IR/Low-Voltage Microcontroller

Z86L70/71/75/C71
IR/Low-Voltage Microcontroller
Zilog
FUNCTIONAL DESCRIPTION (Continued)
HALT. HALT turns off the internal CPU clock, but not the
XTAL oscillation. The counter/timers and external inter-
rupts IRQ0, IRQ1, IRQ2, IRQ3, and IRQ4 remain active.
The devices are recovered by interrupts, either externally
or internally generated. An interrupt request must be exe-
cuted (enabled) to exit HALT Mode. After the interrupt ser-
vice routine, the program continues from the instruction af-
ter the HALT.
STOP. This instruction turns off the internal clock and ex-
ternal crystal oscillation and reduces the standby current
to 10 µA or less. STOP Mode is terminated only by a reset,
such as WDT time-out, POR, SMR, or external reset. This
causes the processor to restart the application program at
address 000CH. In order to enter STOP (or HALT) mode,
it is necessary to first flush the instruction pipeline to avoid
suspending execution in mid-instruction. To do this, the
user must execute a NOP (opcode = FFH) immediately be-
fore the appropriate sleep instruction, i.e.,
FF NOP ; clear the pipeline
6F STOP ; enter STOP Mode
or
FF NOP ; clear the pipeline
7F HALT ; enter HALT Mode
Port Configuration Register (PCON). The PCON regis-
ter configures the comparator output on Port 3. It is locat-
ed in the expanded register file at Bank F, location 00 (Fig-
ure 32).
PCON (FH) 00H
D7 D6 D5 D4 D3 D2 D1 D0
* Default Setting After Reset
Comparator Output Port 3
0 P34,Standard Output*
1 P34,Comparator Output
Reserved (Must be 1)
Figure 32. Port Configuration Register (PCON)
(Write Only)
1-42
PRELIMINARY
DS97LVO0500