Z90102 Datasheet, PDF (33/36 Pages) Zilog, Inc. – 40-Pin Low-Cost Digital Television Controller

Zilog
Z90102/90103/90104
40-Pin Low-Cost Digital Television Controller
R250 IRQ
FAH
D7 D6 D5 D4 D3 D2 D1 D0
Reset Condition = 00H
IRQ - Software only
IRQ1 - VSYNC
IRQ2 - P31 Input
IRQ3 - P30 Input
IRQ4 - T0
IRQ5 - T1
Reserved (Must be 0)
Figure 62. Interrupt Request Register
(FAH: Read/Write)
R251 IMR
FBH
D7 D6 D5 D4 D3 D2 D1 D0
* Default after Reset
1 - Enables IRQ5 - IR0
(D0 - IRQ0)
Reserved (Must be 0)
1 - Enables Interrupts
0* Disable Interrupts
Figure 63. Interrupt Mask Register
(FBH: Read/Write)
R252 FLAGS
FCH
D7 D6 D5 D4 D3 D2 D1 D0
User Flag F1
User Flag F2
Half Carry Flag
Decimal Adjust Flag
Overflow Flag
Sign Flag
Zero Flag
Carry Flag
R253 RP
FDH
D7 D6 D5 D4 D3 D2 D1 D0
1
Reset Condition = 00H
Reserved (Must be 0)
Register Pointer
Figure 65. Register Pointer
(FDH: Read/Write)
R254 GP
FEH
D7 D6 D5 D4 D3 D2 D1 D0
Reset Condition = Undefined
0 = Level 0
1 = Level 1
Figure 66. General-Purpose
(FEH: Read/Write)
R255 SPL
FFH
D7 D6 D5 D4 D3 D2 D1 D0
Stack Pointer Upper
Byte (SP7-SP0)
Figure 67. Stack Pointer
(FFH: Read/Write)
Figure 64. Flag Register
(FCH: Read/Write)
DS97TEL1902
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