Z90102 Datasheet, PDF (23/36 Pages) Zilog, Inc. – 40-Pin Low-Cost Digital Television Controller

Zilog
Z90102/90103/90104
40-Pin Low-Cost Digital Television Controller
Watch-Dog Timer (WDT). The Z90102/3/4 is equipped If the WDH instruction is used, and if the HALT Mode is not
with a permanently enabled Watch-Dog Timer which must released and the Watch-Dog Timer is not retriggered (by
1 ^{be refreshed every 12 ms. Failure to refresh the timer re- the WDT instruction) within 12 ms, a device reset occurs.}
sults in a reset of the device. The WDT is permanently en- The WDT instruction affects the Z (Zero) S (Sign), and V
abled and is initially reset upon POR. Every subsequent (Overflow) flags. WDT does not run during STOP Mode.
WDT instruction resets the timer. The Watch-Dog Timer
may or may not be enabled during the STOP Mode. The ^VCC ^{Voltage Sensitive Reset (VSR). Reset is globally}
instruction WDT 4F (HEX) enables the timer during HALT. ^{driven if V}CC ^{is below the specified voltage (Figure 21).}
VBO 3.80
3.60
3.40
3.20
3.00
2.80
2.60
2.40
-60 -40 -20 +0 20 40 60 80 100 120 140
Temperature
(°C)
Figure 21. Voltage Sensitive Reset vs Temperature
DS97TEL1902
23