Z90102 Datasheet, PDF (18/36 Pages) Zilog, Inc. – 40-Pin Low-Cost Digital Television Controller

Z90102/90103/90104
40-Pin Low-Cost Digital Television Controller
Zilog
FUNCTIONAL DESCRIPTION (Continued)
Memory Mapped Register. All control registers and I/O
ports (except Port 2 and Port 3) are assigned to program
memory space. Address space FC00H contains OSD con-
trol registers, PWM output registers and Port 6 I/O regis-
ters. Two bits of the decoded AFCIN port are assigned to
Port 6 input port. LDE and LDEI instructions are required
to transfer data between the Register File and the Memory
Mapped Registers.
Register File. A total of 253 byte registers are implement-
ed in the Z8 core. Address 00H, 01H and FOH are re-
served. The register file consists of two I/O Port registers,
236 general-purpose registers and 15 control and status
registers (Figure 19). The instructions can access regis-
ters directly or indirectly with an 8-bit address field. This
also allows short 4-bit register addressing using the Reg-
ister Pointer. In the 4-bit mode, the register file is divided
into sixteen working-register groups, each occupying 16
continuous locations. The Register Pointer addresses the
starting location of the active working-register group (Fig-
ure 15).
Note: Register Bank E0-EF is only accessed through a
working register and indirect addressing modes.
r7 r6 r5 r4
r3 r2 r1 r0 R253
(Register Pointer)
The upper nibble of the register file address
provided by the register pointer specifies
the active working-register group.
FF
Register Group F
F0
•
•
•
•
•
•
•
•
R15 to R0
Hex
Address
02
Port 2 (P2)
03
Port 3 (P3)
04
General-Purpose
Registers
EF
F0
Reserved
F1
Timer Mode (TMR)
F2
Timer/Counter1(T1)
F3
T1 Prescaler (PRE1)
F4
Timer/Counter0 (T0)
F5
T0 Prescaler (PRE0)
F6
Port 2 Mode (P2M)
F7
Port 3 Mode (P3M)
F8
Port 0-1 Mode (P01M)
F9
Interrupt Priority Reg (IPR)
FA
Interrupt Request Reg (IRQ)
FB
Interrupt Mask Reg (IMR)
FC
Condition Flag (FLAGS)
FD
Register Pointer (RP)
FE
Stack Pointer High (SPH)
FF
Stack Pointer Low (SPL)
•
•
•
•
•
Specified Working
•
Register Group
2F
20
1F
Register Group 1
10
0F
Register Group 0
I/O Ports
00
The lower nibble
of the register
file address
provided by the
instruction points
to the specified
register.
R15 to R0
R15 to R4
R3 to R0
Figure 16. Register Pointer
Figure 15. Register File Configuration
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DS97TEL1902