Z90102 Datasheet, PDF (22/36 Pages) Zilog, Inc. – 40-Pin Low-Cost Digital Television Controller

Z90102/90103/90104
40-Pin Low-Cost Digital Television Controller
FUNCTIONAL DESCRIPTION (Continued)
HALT Mode. The Z90102/3/4 is driven by two internal
clocks, TCLK and SCLK. They both oscillate at the crystal
frequency. TCLK provides the clock signal for the counter-
timers and the interrupt block. SCLK provides the clock
signal for all other CPU blocks. HALT Mode turns off the
internal CPU clock (SCLK), but not the XTAL oscillation.
The counter/timers and external interrupts remain active.
The device may be recovered by interrupts, either exter-
nally or internally generated. An interrupt request may be
executed (enabled) to exit HALT Mode. After the interrupt
service routine, the program continues from the instruction
after the HALT.
STOP Mode. The STOP instruction stops crystal oscilla-
tion, thereby stopping both SCLK and TCLK. The device
ceases to operate. The STOP Mode can be released by
two methods. The first method is to reset the device. A
high input condition on Port 3 P30 is the second method.
After releasing the STOP Mode by using either one of the
two methods, program execution begins at location
000CH. To complete an instruction prior to entering the
standby modes, a NOP instruction has to be placed before
Zilog
the HALT or STOP instructions. This is required because
of instruction pipelining, i.e.:
FF NOP
6F STOP
FF NOP
7F HALT
; clear the pipeline
; enter STOP Mode
or
; clear the pipeline
; enter HALT Mode
Notes: In STOP Mode, XTAL2 pin has an internal pull-up
on it and OSCOUT has an internal pull-down.
Clock. The Z90102/3/4 on-chip oscillator has a high-gain,
parallel-resonant amplifier for connection to a crystal, ce-
ramic resonator, or any suitable external clock source
(XTAL1 = Input, XTAL2 = Output). The crystal is an AT cut,
parallel resonant, 4 MHz max with a series resistance (RS)
less than or equal to 100 Ohms.
The crystal source is connected across XTAL1 and XTAL2
using the crystal manufacturer's recommended capacitors
(10 pF < CL < 300 pF, where C1=C2=CL) from each pin to
device ground (Figure 20).
C1
* VSS
XTAL1
C2
* VSS
XTAL2
Ceramic Resonator
or Crystal
XTAL1
XTAL2
External Clock
XTAL1
27mH
6.8kW
33pF
* VSS
33pF
* VSS
LC Oscillator Circuits
XTAL2
MPU
* Must be connected to VSS pin and not
system ground.
Figure 20. Oscillator Configuration
22
DS97TEL1902