Z90102 Datasheet, PDF (17/36 Pages) Zilog, Inc. – 40-Pin Low-Cost Digital Television Controller

Zilog
Z90102/90103/90104
40-Pin Low-Cost Digital Television Controller
Program Memory. The program ROM size is 6 KB (Figure vector address. IRQ1 vector is fixed to VSYNC interrupt re-
14). The IRQ vector table is located in the lower address quest and occurs at the leading edge of the filtered VSYNC
1 ^{space. The vector address is fetched after the correspond- input. Program memory start at address 000CH after re-}
ing interrupt and program control is passed to the specified set.
Hex
Address
0000
0001
0002
0003
0004
0005
0006
0007
0008
0009
000A
000B
000C
¯
17FF
1800
¯
FBFF
FC00
¯
FC32
FC33
¯
FCFF
FD00
¯
FDB4
FDB5
¯
FFFF
IRQ0 (High Byte)
IRQ0 (Low Byte)
VSYNC IRQ1 (High Byte)
VSYNC IRQ1 (Low Byte)
P31 IRQ2 (High Byte)
P31 IRQ2 (Low Byte)
P30 IRQ3 (High Byte)
P30 IRQ3 (Low Byte)
T0 IRQ4 (High Byte)
T0 IRQ4 (Low Byte)
T1 IRQ5 (High Byte)
T1 IRQ5 (Low Byte)
Reset Start Address
On-Chip Program ROM
(6 KByte)
Reserved
Memory Mapped I/O
Reserved
Video Refresh RAM
Reserved
Hex
Address
OSD Control (OSD_CNTRL)
Vertical Position (VERT_POS)
Horizontal Position (HOR_POS)
Display Attribute (DISP_ATTR)
Row Space (ROW_SPACE)
Fade Position (FADE_POS)
Bar Line Control (BAR_CNTRL)
Bar Position (BAR_POS)
FC00
FC01
FC02
FC03
FC04
FC05
FC06
FC07
PWM Mode (PWM_MODE)
PWM Output Port (PWM_OUT)
PWM1 High 6-Bit (PWM1_HI)
PWM1 Low 8-Bit (PWM_LO)
Reserved
PWM6 6-Bit Register (PWM6)
PWM7 6-Bit Register (PWM7)
PWM8 6-Bit Register (PWM8)
PWM9 8-Bit Register (PWM9)
PWM10 8-Bit Register (PWM10)
PWM11 8-Bit Register (PWM11)
Reserved
FC10
FC11
FC12
FC13
FC14
FC15
FC16
FC17
FC18
FC19
FC1A
FC1B
FC1C
FC1D
FC1E
FC1F
Reserved
Reserved
Port 6 Input Port (PORT6)
FC30
FC31
FC32
Figure 14. Program Memory
Write
Only
DS97TEL1902
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