Z86E09 Datasheet, PDF (23/38 Pages) Zilog, Inc. – Z8 CMOS OTP Microcontrollers

Z86E02/E04/E08/E09 SL1995
Z8 CMOS OTP Microcontrollers
18
Table 11. OPTION BIT PROGRAM AND VERIFY Mode Entry Conditions (Continued)
CE
NC
OE
EPM
V_PP
CLEAR
CLOCK
PGM
Pin 7
Pin 6
Pin 8
Pin 9
Pin 10
Pin 11
Pin 12
Pin 13
Pin 8
Pin 7
Pin 9
Pin 10
Pin 11
Pin 12
Pin 13
Pin 14
V_IL
No Connection
See Figure 11
See Figure 11
See Figure 11
See Figure 11
See Figure 11
V_IH
OPTION BIT PROGRAM AND VERIFY Mode Operation
1. Perform the Option Bit READ/WRITE Mode Entry operation (see OPTION BIT
PROGRAM AND VERIFY Mode Entry on page 16) before proceeding to Step 2.
2. The CLOCK is pulsed High to V_IH, then Low to V_IL. Please refer to Table 14 for
minimum and maximum widths of the CLOCK signal. See Figure 12 and
Table 12.
3. The 8 option bit values required in Table 10 are forced onto Port2. Option bits
D0 to D7 corresponds to Port2 pins P20 to P27. Please refer to Table 14 for
setup and hold times.
4. The PROGRAM operation is performed by lowering PGM to V_IL. Please refer
to Table 14 for minimum and maximum widths of the PGM signal. See
Figure 12 and Table 12.
5. The PROGRAM operation is complete when the PGM is raised back to V_IH.
6. The VERIFY operation is performed by lowering OE to V_IL, then reading the
data on Port2. Pins P20 to P27 represent the Option Bit data D0 to D7,
respectively.
7. A V_OH-level READ on Port2 corresponds to a 1 state (unprogrammed), while
a V_OL level corresponds to a 0 level stored in the EPROM array.
Note: Please refer to Table 14 for the minimum and maximum width of OE dur-
ing EPROM READ mode and data access time.
8. If the data read shows that the address location is not yet programmed, then
repeat Steps 4 to 7 until the data read shows that the address location is
programmed.
PS009201-0301
Programming Specification