Z86E09 Datasheet, PDF (17/38 Pages) Zilog, Inc. – Z8 CMOS OTP Microcontrollers

Z86E02/E04/E08/E09 SL1995
Z8 CMOS OTP Microcontrollers
12
Table 7. EPROM ARRAY READ/WRITE Mode Entry Conditions (Continued)
EPROM Signal
CLEAR
CLOCK
PGM
18-Pin DIP/SOIC
Pin 11
Pin 12
Pin 13
20-Pin SSOP
Pin 12
Pin 13
Pin 14
Forced State
See Figure 8
V_IL
V_IH
EPROM ARRAY READ Mode Operation
1. Perform Steps 1 through 6 of the EPROM ARRAY READ/WRITE mode entry
(see the EPROM ARRAY READ/WRITE Mode Entry operation, previous
page) before proceeding to Step 2.
2. Reset the address counter by pulsing the CLEAR pin. See Figure 9 and
Table 8. Please refer to Table 14 for minimum and maximum widths of the
CLOCK and CLEAR signals.
3. The address counter is incremented on the rising edge of the CLOCK signal.
4. After resetting the address counter using the CLEAR pin, the address counter
points to address 0000h.
5. The READ operation is performed by lowering OE to V_IL and reading the data
on Port2. Pins P20 to P27 represent the EPROM data D0 to D7, respectively.
See Figure 9 and Table 8.
6. A V_OH-level READ on Port2 corresponds to a 1 state, while a V_OL level
corresponds to a 0 level stored in the EPROM array.
Note: Please refer to Table 14 for the minimum and maximum width of OE dur-
ing EPROM READ mode and data access time.
7. The next address is read by pulsing the clock pin High, then forcing OE to V_IL
and bringing it back High after the data is read.
8. Repeat Step 7 until the final address is read.
9. Because the address is sequentially accessed, a previously-accessed
address can only be read by resetting the address counter to 0000h and
clocking the address counter to increment to the appropriate address.
PS009201-0301
Programming Specification