Z86E09 Datasheet, PDF (19/38 Pages) Zilog, Inc. – Z8 CMOS OTP Microcontrollers

Z86E02/E04/E08/E09 SL1995
Z8 CMOS OTP Microcontrollers
14
Table 8. EPROM ARRAY READ Mode Conditions (Continued)
CLEAR
CLOCK
PGM
Pin 11
Pin 12
Pin 13
Pin 12
Pin 13
Pin 14
See Figure 9
See Figure 9
V_IH
EPROM ARRAY PROGRAM AND VERIFY Mode Operation
1. Perform the EPROM ARRAY READ/WRITE mode entry (see the EPROM
ARRAY READ/WRITE Mode Entry operation on page 10) before proceeding
to Step 2.
2. Reset the address counter by pulsing the CLEAR pin. See Figure 10 and
Table 9. Please refer to Table 14 for minimum and maximum widths of the
CLOCK signal.
3. The address counter is incremented on the rising edge of the CLOCK signal.
4. After resetting the address counter using the CLEAR pin, the address counter
points to address 0000h.
5. The PROGRAM operation is performed by lowering PGM to V_IL. See
Figure 10. Please refer to Table 14 for minimum and maximum widths of the
PGM signal.
6. The PROGRAM operation is complete when PGM is raised back to V_IH.
7. The VERIFY operation is performed by lowering OE to V_IL and reading the
data on Port2. Pins P20 to P27 represent the EPROM data D0 to D7,
respectively.
8. A V_OH-level READ on Port2 corresponds to a 1 state, while a V_OL level
corresponds to a 0 level stored in the EPROM array.
9. Please refer to Table 14 for the minimum and maximum width of OE during
EPROM Read mode and data access time.
10. If the data read shows that the address location is not yet programmed, then
repeat Steps 5 to 7 until the data read shows that the address location is
programmed.
11. If the address location is not programmed after the 25th try, then the device is
considered failed.
12. If the address location is programmed, then the address location is
overprogrammed with three times the total accumulated program time.
13. The next address is accessed by pulsing the CLOCK High to V_IH, then Low to
V_IL.
PS009201-0301
Programming Specification