MT9072 Datasheet, PDF (46/275 Pages) Zarlink Semiconductor Inc – Octal T1/E1/J1 Framer

MT9072
Data Sheet
5.1.1 T1 D4 Framing
For D4 links the S-bit position contains an alternating 101010... pattern inserted into every second S-bit. These bits
are intended for determination of frame boundaries, and they are referred to as Ft bits. A separate fixed pattern,
repeating every superframe, is interleaved with the Ft bits. This fixed pattern (001110) is used to delineate the 12
frame superframe. These bits are referred to as the Fs bits. In D4 frames # 6 and #12, the LSB of each channel
byte may be replaced with A bit (frame #6) and B bit (frame #12) signaling information. See Table 8.
Frame #
1
2
3
4
5
6
7
8
9
10
11
12
Ft
Fs
1
0
0
0
1
1
0
1
1
1
0
0
Table 8 - D4 Superframe Structure (T1)
Signaling
A
B
5.1.2 T1 ESF Framing
For ESF links the 6 bit framing pattern 001011, inserted into every 4th S-bit position, is used to delineate both frame
and superframe boundaries. Frames #6, 12, 18 and 24 may contain the A, B, C and D signaling bits, respectively. A
4 kHz data link is embedded in the S-bit position, interleaved between the framing pattern sequence (FPS) and the
transmit CRC-6 remainder (from the calculation done on the previous superframe). See Table 9.
Frame #
1
2
3
4
5
6
7
FPS
FDL
CRC
X
CB1
X
0
X
CB2
X
Table 9 - ESF Superframe Structure (T1)
Signaling
A
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