MT9072 Datasheet, PDF (135/275 Pages) Zarlink Semiconductor Inc – Octal T1/E1/J1 Framer

MT9072
Data Sheet
Bit
Name
Functional Description
15 D4YALML D4 Yellow Alarm Latch. This bit is set if a D4 yellow alarm is detected within a 600
millisecond integration period. This bit is cleared after a read of Y25 or Y35.
14 D4Y48L D4 Yellow Alarm (48 milliseconds) Latch. This bit is set if a D4 yellow alarm is detected
within a 48 millisecond integration period. This bit is cleared after a read of Y25 or Y35.
13 SECYELL Secondary D4 Yellow Alarm Latch. This bit is set if Secondary yellow alarm D4 (S bit in
12 th frame) is detected. It is cleared after a read.This bit is cleared after a read of Y25 or
Y35.
12 ESFYELL ESF Yellow Alarm Latch. This bit is set upon receipt of a ESF yellow alarm. This bit is
cleared after a read of Y25 or Y35.
11 T1DMYL T1DM Yellow Alarm Latched. If this bit is 1 a T1DM yellow alarm is received on bit 2 of
24th timeslot. This bit is cleared after a read of Y25 or Y35.
10
#
not used.
9
BPVL Bipolar Violation Latch. This bit is set when a bipolar violation occurs. This bit is cleared
after a read of Y25 or Y35.
8
PRBSL PRBS Latch. This bit is set when a PRBS error has occured.This bit is cleared after a
read of Y25 or Y35.
7
PDVL Pulse Density Violation Latch. This bit is set when the receive PDV is detected.This bit
is cleared after a read of Y25 or Y35.
6
LLEDL Line Loopback Enable Detect Latch. This bit is set upon receipt of a line loopback
enable code. It is cleared after a read. This is a latched version of LLED(Y10).This bit is
cleared after a read of Y25 or Y35.
5
LLDDL Line Loopback Disable Detect Latch. This bit is set upon receipt of a line loopback
disable code. It is cleared after a read. This is a latched version of LLDD(Y10).This bit is
cleared after a read of Y25 or Y35.
4
BOML Bit Oriented Message Latch. This bit is set if a bit oriented message has been received.
It is cleared upon a read.This bit is cleared after a read of Y25 or Y35.
3
BOMML Bit Oriented Message Match Latch. This bit is set if the bit oriented message received
matches the value of the Bit Oriented Match register.This bit is cleared after a read of Y25
or Y35.
2
CASRL Channel Associated signaling Received Latch. This bit is set if the received CAS has
changed on any of the 24 channels.This bit is cleared after a read of Y25 or Y35.
1
1SECL 1 Second Latch. This bit is set if the one second timer expires. This bit is cleared after a
read of Y25 or Y35.
0
2SECL 2 Second Latch. This bit is set if the two second timer expires. This bit is cleared after a
read of Y25 or Y35.
Table 97 - Receive Line Status and Timer Latch(Y25) (T1)
135
Zarlink Semiconductor Inc.