MT9072 Datasheet, PDF (208/275 Pages) Zarlink Semiconductor Inc – Octal T1/E1/J1 Framer

MT9072
Data Sheet
Bit Name
Functional Description
8
CEIM CRC-4 Error Counter Indication Mask. This is the mask bit for the CEII interrupt status bit in
(0) the Counter (Counter Indication and Counter Overflow) Interrupt Status Register (address
Y35). If this mask bit is one, the corresponding interrupt bit will remain inactive. If this mask bit
is zero, the corresponding interrupt bit will function normally.
7
VEOM Bipolar Violation (BPV) Error Counter Overflow Mask. This is the mask bit for the VEOI
(0) interrupt status bit in the Counter (Counter Indication and Counter Overflow) Interrupt Status
Register (address Y35). If this mask bit is one, the corresponding interrupt bit will remain
inactive. If this mask bit is zero, the corresponding interrupt bit will function normally.
6
VEIM Bipolar Violation (BPV) Error Counter Indication Mask. This is the mask bit for the VEII
(0) interrupt status bit in the Counter (Counter Indication and Counter Overflow) Interrupt Status
Register (address Y35). If this mask bit is one, the corresponding interrupt bit will remain
inactive. If this mask bit is zero, the corresponding interrupt bit will function normally.
5
EEOM E-Bit Error Counter Overflow Mask. This is the mask bit for the EEOI interrupt status bit in
(0) the Counter (Counter Indication and Counter Overflow) Interrupt Status Register (address
Y35). If this mask bit is one, the corresponding interrupt bit will remain inactive. If this mask bit
is zero, the corresponding interrupt bit will function normally.
4
EEIM E-Bit Error Counter Indication Mask. This is the mask bit for the EEII interrupt status bit in
(0) the Counter (Counter Indication and Counter Overflow) Interrupt Status Register (address
Y35). If this mask bit is one, the corresponding interrupt bit will remain inactive. If this mask bit
is zero, the corresponding interrupt bit will function normally.
3 PCOM PRBS CRC-4 Counter Overflow Mask. This is the mask bit for the PCOI interrupt status bit
(0) in the Counter (Counter Indication and Counter Overflow) Interrupt Status Register (address
Y35). If this mask bit is one, the corresponding interrupt bit will remain inactive. If this mask bit
is zero, the corresponding interrupt bit will function normally.
2
(0) not used.
1
PEOM PRBS Error Counter Overflow Mask. This is the mask bit for the PEOI interrupt status bit in
(0) the Counter (Counter Indication and Counter Overflow) Interrupt Status Register (address
Y35). If this mask bit is one, the corresponding interrupt bit will remain inactive. If this mask bit
is zero, the corresponding interrupt bit will function normally.
0
PEIM PRBS Error Counter Indication Mask. This is the mask bit for the PEII interrupt status bit in
(0) the Counter (Counter Indication and Counter Overflow) Interrupt Status Register (address
Y35). If this mask bit is one, the corresponding interrupt bit will remain inactive. If this mask bit
is zero, the corresponding interrupt bit will function normally.
Table 183 - Counter (Counter Indication and Counter Overflow) Interrupt Mask Register (Address Y45)
(E1)
208
Zarlink Semiconductor Inc.