MT9072 Datasheet, PDF (181/275 Pages) Zarlink Semiconductor Inc – Octal T1/E1/J1 Framer

MT9072
Data Sheet
Bit Name
Functional Description
1
E4CK Extracted 4 Data Link Clock. If one, the RxDLC pin outputs an ST-BUS type 4.096 MHz
(0) clock signal derived from a doubled 2.048 MHz clock signal at the EXCLi pin. This clock is
synchronous with the receive data before it passes through the elastic buffer at the RxDL pin,
or at the DSTo pin if control bit ELAS (register address Y03) is disabled. If zero, the RxDLC pin
operates as a receive data link clock or enable signal as programmed by control bit DLCK
(register address Y08).
0
DLCK Data Link Clock. If one, the TxDLC and RxDLC pins output a gapped clock. If zero, the
(0) TxDLC and RxDLC pins output an active low enable signal. The above only applies for the
national bits enabled for DL pin operation (by the Sa4-8 bits of register address Y03). See
Figures 30 to 34.
Table 150 - DataLink Control Register (R/W Address Y08) (E1)
Bit Name
Functional Description
15-8 # not used.
7-0 RXIDC Receive Idle Code. This is the idle code that is sent on the DSTochannels if the per timeslot
7-0 control bit MPDR is set(Y90-YAF). Note that bit 7 is sent out first.
(0)
Table 151 - Receive Idle Code Register(Y09) (E1)
Bit Name
Functional Description
15-8 # not used.
7-0 TXIDC Transmit Idle Code. This is the idle code that is sent on the PCM30 channels if the per timeslot
7-0 control bit MPDT is set(Y90-YAF)
(0)
Table 152 - Transmit Idle Code Register(Y0A) (E1)
17.2.4 Master Status Registers (Y10 - Y1A) Bit Functions
Tables 158 to 172 describe the bit functions of each of the Master Status Registers in the MT9072 in E1 mode.
Each register is repeated for each of the 8 framers. Framer 0 is addressed with Y=0, Framer 1 with Y=1, Framer 2
with Y=2 and so on up to Framer 7 with Y=7 (where Y represents the 4 most significant address bits (MSB)
A11-A8).
181
Zarlink Semiconductor Inc.