EA218E Datasheet, PDF (16/28 Pages) Zarlink Semiconductor Inc – EA218E 8-Port Ethernet Access Controller XpressFlow 2020 Ethernet Routing Switch Chipset

PRELIMINARY
XpressFlow-2020 Series –
Ethernet Switch Chipset
INFORMATION
EA218E
8-Port 10Mb Ethernet Access Controller
2.3 XpressFlow Bus Operation
Zarlink’s optimized XpressFlow Bus architecture
Provides 1.6G bps switching bandwidth
9 -33
1.07G bps
9 -40
1.28G bps
9 -50
1.6G bps
Full multi bus master structure
Allows XpressFlow Engine to communicate with Access Con-
trollers via a message passing protocol
9 Command Messages for passing control information be-
tween devices
9 Data Messages for forwarding an Ethernet frame from re-
ceiving port to transmission port
Built-in intelligent bus load regulator for data traffic balancing
Provides centralized bus arbitration with two level request pri-
orities
9 High priority for Data Messages
9 Low priority for Command Messages
2.3.1 Pin Description
Symbol
S_D[31:0]
S_MSGEN#
S_EOF#
S_IRDY
S_TABT#
S_HPREQ#
S_REQ#
S_GNT#
S_OVLD#
S_CLK
Type Name and Functions
CMOS
I/O-TS
CMOS
I/O-TS
CMOS
I/O-TS
CMOS
I/O-TS
Data Bus Bit [31:0] – a 32-bit synchronous data bus.
Note: During the system RESET period, Data Bit [31:28] are used as Processor Interface
Configuration bit [0:3]
Message Envelope – encompasses the entire period of a message transfer. Targets use the
leading edge of this signal to detect the beginning of a message transfer, and to decode the
message header for the intended target(s).
End of Frame – only used by frame data transfer messages to identify the end of frame condi-
tion. This signal is synchronous with the Rx Frame Status word appended to the end of the
message.
Initiator Ready – a normal true signal. When negated, it indicates the initiator had asserted wait
state(s) in between command words. Target should use this signal as enable signal for latching
the data from the bus.
CMOS Target Abort – when asserted, the target had aborted the reception of current message on the
I/O-OD bus.
CMOS High Priority Request – indicates one or more Bus Requester is requesting for high priority
I/O-OD message transfer.
CMOS Bus Request –Bus Request signals from Access Controller to Bus Access Arbitrator in Xpress-
Output Flow Engine
CMOS In- Bus Grant –Bus Grant signals from Bus Arbitrator to Bus Requester
put
CMOS Bus Overload – when asserted, all data forwarding bus bandwidth has been allocated. Cannot
Output support additional load for data forwarding traffic.
CMOS XpressFlow Bus Clock – 33MHz system clock
Input
© 1998 Zarlink Semiconductor, Inc.
15
Rev.2.1 – February, 1999