EA218E Datasheet, PDF (14/28 Pages) Zarlink Semiconductor Inc – EA218E 8-Port Ethernet Access Controller XpressFlow 2020 Ethernet Routing Switch Chipset

PRELIMINARY
XpressFlow-2020 Series –
Ethernet Switch Chipset
INFORMATION
EA218E
8-Port 10Mb Ethernet Access Controller
2.2.5 Register Map
Note: All 32-bit registers are D-word aligned.
All 16-bit registers are also D-word aligned and right justified.
For the Little Endian CPUs, register offset bit [1,0] are always set to be 00.
For the Big Endian CPUs, register offset bit [1,0] are always set to be 10.
This is a Global Register. CPU is allowed to write the Global Register of all devices by a single operation.
These registers are reserved for system diagnostic usage only.
Register Description
Device Configuration Registers (DCR)
GCR
Global Control Register
DCR0
DCR1
DCR2
DCR3
DCR4
DTSR
Device Status Register
Signature & Revision Register
ID Register
Device Configuration Register
Interfaces Status Register
Test Register
Interrupt Controls
ISR
Interrupt Status Register – Unmasked
ISRM
Interrupt Status Register – Masked
IMSK
Interrupt Mask Register
IAR
Interrupt Acknowledgment Register
Buffer Memory Interface
MWAR Memory Write Address Reg. – Single Cycle
MRAR Memory Read Address Reg. – Single Cycle
MBAR Memory Address Register – Burst Mode
MWBS Memory Write Burst Size (in D-words)
MRBS Memory Read Burst Size (in D-words)
MWDR Memory Write Data Register
MWDX Memory Write Data Reg. – Byte Swapping
MRDR Memory Read Data Register
MRDX Memory Read Data Reg. – Byte Swapping
FCB Buffer & Stack Management
FCBBA Frame Control Buffer – Base Address
FCBAG Frame Control Buffer – Buffer Aging Status
FCBSL
FCBST
FCBSS
Frame Ctrl Buffer Stack – Size Limit
Frame Ctrl Buffer Stack – Buffer Low Threshold
Frame Ctrl Buffer Stack – Allocation Status
I/O Offset
Little Big Reg.
Endian Endian Size
W/R Note:
hF00 hF02 16-bit W/--
hF00 hF02 16-bit --/R
hF10 hF12 16-bit --/R
hF20 hF22 16-bit W/R
hF30 hF32 16-bit W/R
hF40 hF42 16-bit --/R
hF70 hF72 16-bit W/R
hF80 hF82 16-bit --/R
hF90 hF92 16-bit --/R
hFA0 hFA2 16-bit W/R
hFB0 hFB2 16-bit W/--
hE08 hE08 32-bit W/R
hE18 hE18 32-bit W/R
hE28 hE28 32-bit W/R
hE40 hE42 16-bit W/R
hE50 hE52 16-bit W/R
hE68 hE68 32-bit W/--
hE6C hE6C 32-bit W/--
hE68 hE68 32-bit --/R
hE6C hE6C 32-bit --/R
hD00 hD02 16-bit W/R
hD30 hD32 16-bit --/R
hD90 hD92 16-bit W/R
hDA0 hDA2 16-bit W/R
hDB0 hDB2 16-bit --/R
© 1998 Zarlink Semiconductor, Inc.
13
Rev.2.1 – February, 1999