EA218E Datasheet, PDF (11/28 Pages) Zarlink Semiconductor Inc – EA218E 8-Port Ethernet Access Controller XpressFlow 2020 Ethernet Routing Switch Chipset

PRELIMINARY
XpressFlow-2020 Series –
Ethernet Switch Chipset
INFORMATION
EA218E
8-Port 10Mb Ethernet Access Controller
2.2 Processor Bus Interface
Supports various industry standard micro-processors including:
9 Intel 186, 386, and 486 family or equivalent
9 Motorola MPC series embedded processors
Easily adapts to other industry standard CPUs
Provides separate Address and Data bus
Supports Big & Little Endian byte ordering
Supports 16-bit Data Bus
Supports early RDY cycle
9 Meets timing requirement for Intel/AMD 186 family proc-
essors
Supports 1X or 2X CPU Clock
9 2X CPU Clock for 386 family processors
Provides a single interrupt signal to Switch Manager CPU
2.2.1 Pin Description
Symbol
P_C[4:0]
P_A[11:1]
P_D[15:0]
P_ADS#
P_RWC
P_RDY#
P_BS16#
P_CS#
P_INT
P_RST#
P_CLK
Type
Name and Functions
CMOS Input
Processor Configuration bit [4:0]: – During the Reset Cycle, the P_C[4:0] pins provides the
processor configuration. By using external weak pull-up or -down resistors, they define the Ex-
ternal Management Bus Interface Configuration. These inputs are sampled at the trailing edge of
the Reset cycle.
C[0] – Defines the CPU Clock input is 1X or 2X clock
C[1] – Selects either Big or Little Endian byte ordering
C[2] – Defines the polarity of the P_RWC (Rd/Wr Control) input
C[3] – Defines the CPU Bus width – For EA-208, it is default to 16-bit CPU Bus interface, and
the setting of this bit is ignored.
C[4] – Defines the timing relationship between P_RDY and P_D[15:0] valid. If C[4] is High,
the P_D[15:0] are valid along in the same clock period as P_RDY is asserted. If C[4]
is Low, the P_RDY is asserted one clock period early ahead of the P_D[15:0] are
valid.
C[0]
CPU Clock
C[1]
Byte Order
C[2]
C[3]
C[4]
RWC
Bus Size RDY Timing
Lo 1X Clock
Little Endian P_R/W#
n/a
Hi 2x Clock
Big Endian
P_W/R#
n/a
Normal
Early
After RESET, these pins are used as XpressFlow Bus Data bit [31:27].
TTL In (5VT) Address Bus Bit [11:1] – I/O port address
TTL I/O-TS (5VT) Data Bus Bit [15:0] – a 16-bit synchronous data bus.
TTL In (5VT) Address Strobe – indicates valid address is on the bus
TTL Input (5VT) Read/Write Control – indicates the current bus cycle is a read or write cycle. C[1] defines the
polarity of this signal during the Reset cycle.
C[1]=Low P_R/W# is used for PowerPC or other similar processors.
C[1]=High P_W/R# is used for 386, 486 or other similar processors
TTL Out-OD Data Ready – timing indicates for bus data valid
TTL Out-OD Bus Size 16 – response to bus master that the EA208 only supports 16-bit data bus width.
TTL Input (5VT) Chip Select – indicates the XpressFlow Engine is the target for the current bus operation.
CMOS Output Interrupt Request to Switch Manager CPU The polarity of this signal output is programmable
via chip configuration register.
TTL In-ST (5VT) CPU Reset – Synchronous reset Input from Switch Manager CPU
TTL In (5VT) CPU Clock – 2X Clock for 386 family, and 1X Clock for the others
© 1998 Zarlink Semiconductor, Inc.
10
Rev.2.1 – February, 1999