YSS932 Datasheet, PDF (9/23 Pages) YAMAHA CORPORATION – 96kHz DIR + Dolby Digital / Pro Logic II / DTS decoder + Sub DSP

YSS932
DIRBCK, DIRWCK, FS128, SYNC
The clock for such peripheral devices as DAC and ADC is output.
At CMOD=0 setting, FS128 is output from FS128/C pin and at UMOD=0 setting, SYNC is output from
SYNC/U pin.
DIRBCK, DIRWCK and FS128 are obtained by dividing the clock of DIRMCK and the period of each clock
is as follows.
DIRBCK
DIRWCK
FS128
→ 64fs
→ fs
→ 128fs
SYNC is output according to the following timing.
Note) At settings of DIROWP=0, DIROBP=0
Rch
DIRWCK
DIRBCK
FS128
SYNC
Lch
Lch
Rch
1-3) Serial data output
DIRSDO
The DAIF signal data is output. The output is always 24-bit width including audio auxiliary bit. The data is
output from the DIRSDO pin as well as goes into the Main DSP block through the SDIA interface.
It must be noted that the data output from the DIRSDO pin is muted during the free-run mode or at
SDOMUTE=1 setting, but the data output to the Main DSP is muted only during the free-run mode regardless
of SDOMUTE setting.
The output format can be selected by setting the DIR SDO register. For the details of the format, refer to
"Serial Data Interface Format".
1-4) Status data output
BS, V, U, C
The data of block start, validity flag, user data and channel status obtained from the DAIF signals are output
as described below.
The block start is output from the ERR/BS pin at BSMOD=1 setting.
The validity flag is output from the DBL/V pin at VMOD=1 setting.
The user data is output from the SYNC/U pin at UMOD=1 setting.
The channel status is output from the FS128/C pin at CMOD=1 setting.
BS, V, U, C are fixed to the "L" level during the free-run mode or at VUCMUTE=1 setting.
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