YSS932 Datasheet, PDF (14/23 Pages) YAMAHA CORPORATION – 96kHz DIR + Dolby Digital / Pro Logic II / DTS decoder + Sub DSP

YSS932
4) Microprocessor Interface
/CS, SCK, SI, SO
The control registers are read / written via the four-wire serial microprocessor interface.
For the interface format, refer to "Microprocessor Interface Format".
IPORT0-4, DDIN1-3
The signals input to these pins can be read via the IPORT register.
By connecting the status output of other devices to these pins, it is possible to read the data of other devices
via the microprocessor interface of this device. It should be noted that DDIN1-3 are also used as input signal
pins of DIR block.
IPORT0-4 pins may be left open when unused as pull-up resistors are built-in, but be sure to connect the
unused DDIN1-3 pins to VSS as no pull-up resistors are built-in.
OPORT0-7
The data written in the OPORT register are output from these pins.
By connecting the mode selection of other devices to these pins, the other device can be controlled via the
microprocessor interface of this device.
5) Clock
XI, XO
These are crystal oscillator (24.576MHz) connection pins. Use a crystal oscillator of fundamental mode.
Use XI when inputting the external clock.
CPO
This is to connect external parts for PLL generating the operation clock of the DSP block. Connect a resistor
and capacitors between CPO and AVSS as close as physically possible to CPO.
CPO
470pF
1kΩ
4700pF
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