YSS932 Datasheet, PDF (18/23 Pages) YAMAHA CORPORATION – 96kHz DIR + Dolby Digital / Pro Logic II / DTS decoder + Sub DSP

Serial Data Interface Format
YSS932
Shown below are interface formats obtained by setting SDIA Register, SDOA Register, SDIB Register,
SDOB Register and DIR SDO Register.
WCK
WP=0
WP=1
Lch (Ls,Cch)
1 Frame
Rch (RS,LFEch)
BCK
BP=0
BP=1
No Delay
FMT1-0=00
BIT1-0=XX
M
L
M
L
1 bit Delay
FMT1-0=10
BIT1-0=XX
M
L
M
L
EIAJ
DATA
FMT1-0=01
BIT1-0=00
L
M
87
L
M
87
FMT1-0=01
BIT1-0=01
L
M
65
L
M
65
FMT1-0=01
BIT1-0=10
L
M
43 L
M
43
FMT1-0=01 _L
M
L
M
L
BIT1-0=11
M : MSB L : LSB
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