YSS932 Datasheet, PDF (13/23 Pages) YAMAHA CORPORATION – 96kHz DIR + Dolby Digital / Pro Logic II / DTS decoder + Sub DSP

YSS932
3) Sub DSP Block
3-1) Serial data input / output
SDIB0-3
These are PCM input pins to the Sub DSP block.
The data input to SDIB0-2 pins or the SDOA0-2 output from the Main DSP block are selected at SDIBSEL
and processed in the Sub DSP block. The input data to the SDIB3 pin is always processed in the Sub DSP
block regardless of SDIBSEL.
Refer to "Block Diagram".
The input format can be selected by setting the SDIB register.
For the format, refer to "Serial Data Interface Format".
SDOB0-3
These are the output pins for the PCM signals processed in the Sub DSP block.
The output format can be selected by setting the SDOB register.
For the format, refer to "Serial Data Interface Format".
3-2) External memory interface
RAMA0-17, RAMD0-15, RAMWEN, RAMOEN, CASN, RASN
These pins are used to connect an external memory to the Sub DSP block for the data delay.
3-3) Status output
OVFB/END
The output varies depending on OVFSEL settings of ERAM register bit 7.
This output is used when programming Sub DSP.
OVFB at OVFSEL=0
This pin becomes "H" level when a digital overflow occurs as a result of operation in the Sub DSP block.
"H" level is kept from the moment an overflow occurs to the moment the next PCM sample is output from
the SDOB interface. When the next PCM sample output starts, the pin is reset to "L" level.
END at OVFSEL=1
This pin becomes "H" level while the program counter of Sub DSP is operating, and "L" level when all the
processing is completed and the program counter stops. While operating correctly, it becomes "L" level
once during one sample time. If it fails to become "L" level even once during one sample time, it means
that the program has not been completed correctly and fully.
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