YSS932 Datasheet, PDF (12/23 Pages) YAMAHA CORPORATION – 96kHz DIR + Dolby Digital / Pro Logic II / DTS decoder + Sub DSP

YSS932
2) Main DSP Block
2-1) Serial data input / output
SDIA
This is used to input PCM or bitstream into the Main DSP block. Normally, the PCM output of the external
ADC is input.
The input format can be selected by setting the SDIA register.
For the format, refer to "Serial Data Interface Format".
The SDIA pin input or DIRSDO output of the DIR block is selected by SDIASEL, and processed in the Main
DSP block.
SDOA0-2
The PCM signal processed in the Main DSP block is output to these pins.
L-ch, R-ch signals are output from SDOA0 pin, LS-ch, RS-ch signals from SDOA1 pin and C-ch, LFE-ch
signals from SDOA2 pin.
At the same time the signals are output from these pins, they are input to the Sub DSP block through the
SDIB interface.
The output format can be selected by setting the SDOA register.
For the format, refer to "Serial Data Interface Format".
SDBCKI0, SDWCKI0, SDBCKI1, SDWCKI1
These are input clocks for the serial data. When the serial data is synchronized not to DIRBCK, DIRWCK
from DIR included in this LSI but to the clocks from the outside, supply clocks to these pins.
The clocks for the SDIA / SDOA interface will be DIRBCK / DIRWCK or SDBCKI0 / SDWCKI0 selected
at SDIACKSEL.
The clocks for the SDIB / SDOB interfaces will be the same clocks for the SDIA interface
(DIRBCK / DIRWCK or SDBCKI0 / SDWCKI0 selected at SDIACKSEL)
or
SDBCKI1 / SDWCKI1
(Refer to "Block Diagram".)
When not using the external clock, keep these pins unconnected.
/SDBCKO
A reverse clock of DIRBCK or SDBCKI0 selected at SDIACKSEL is output. This clock can be utilized when
the polarity of the clock for the peripheral devices such as ADC and DAC differs.
Refer to "Block Diagram".
2-2) Status output
DTSDATA, AC3DATA, SURENC, KARAOKE, MUTE, CRC, NONPCM
These pins output the status data of the signals processed in the Main DSP block.
The status, which is the same as the contents of the STATUS Register, is output from respective pins.
ZEROFLG
This pin indicates how long the input signal (SDIA or DIRSDO) for the Main DSP block is kept in the digital
zero state. The same status as ZEROFLG of the ZERO Register is output.
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