YGV628B Datasheet, PDF (3/26 Pages) YAMAHA CORPORATION – AVDP7 Advanced Video Display Processor 7

YGV628B






■ Block Diagram
Video Input I/F
DRI[5:0]
DGI[5:0]
DBI[5:0]
HSIN_N
VSIN_N
GCK1IN
GCK2IN
Video Memory I/F
SDQ[15:0]
SA[13:0]
SCS_N
RAS_N
CAS_N
WE_N
UDQM
LDQM
SDCKOUT
CPU I/F
D[15:0]
A[23:1]
CS_N
WRH_N
WRL_N
RD_N
WAIT_N
READY_N
INT_N
DREQ_N
RESET_N
To Clock Gen.
To CRTC
Data
FORMAT
CONV.
Bitmap
FIFO
Data
FORMAT
CONV.
FILTER
PRIORITY
ENC.
Alpha
Blending
Data
FORMAT
CONV.
DAC
DAC
DAC
Monitor I/F
R, G, B
DRO5-0
DGO5-0
DBO5-0
IREF
CSYNC_N
VSYNC__NN
BLANK_N
GCK1OUT
GCK2OUT
DMA
Control
CPU Interface
Color Palette
RReeggiissters
CRTC
TTo all blockss
Clock
Clock Gen.
SYCKIN
■ Examples of System Composition
z Independent (self-propelled) system
RAM
ROM
CPU
AVDP7
Dot clock
SDRAM
Analog RGB
Digital RGB
CRT
LCD
Encoder
z Example of OSD to Digital Image (CPU, SDRAM, etc. are omitted)
External Image
[16bitYCrCb]
[ITU656]
AVDP7
Image + OSD
[16bitYCrCb]
[ITU656]
Composite
Separate
DAC NTSC Encoder
Component
-3-