YGV628B Datasheet, PDF (20/26 Pages) YAMAHA CORPORATION – AVDP7 Advanced Video Display Processor 7

YGV628B






● SDRAM Interface (Measurement Condition: CL=15pF)
No.
Item
1 SDCKOUT: jitter
SDCKOUT: frequency
2
SDCKOUT: cycle time
3 SDCKOUT: clock high level width
4 SDCKOUT: clock low level width
5 SDQ15-0 : input data setup time
6 SDQ15-0 : input data hold time
7
SCS_N, RAS_N, CAS_N, WE_N, SA13-0,
SDQ15-0, UDQM, LDQM : output delay time
8
SCS_N, RAS_N, CAS_N, WE_N, SA13-0,
SDQ15-0, UDQM, LDQM : output hold time
Symbol
t_jSDCK
f_SDCK
t_cSDCK
t_whSDCK
t_wlSDCK
t_sSDQ
t_hSDQ
t_dSDO
t_hSDO
Min
-1
75
12.35
3.5
3.5
4
1
1.5
Typ
Max
Unit Note
1
ns
1
81
MHz
1,2
13.33
1,3
1
1
1
ns
1
9
1
1
Contents of Mode Register
Read/Write Mode
Burst Read and Burst Write
CAS Latency
2
Wrap Type
Sequential
Burst Length
2
Command Interval
4
Clock Cycle Time (C_L=2)
Ref/Active – Ref/Active Command
Interval
t_CK2 Less than 10 ns
t_RC
Six or less cycle
(in case of SDCKOUT frequency 81 MHz, less than 74ns)
5
Pre-charge – Active Command Interval
t_RP
Two or less cycle
(in case of SDCKOUT frequency 81 MHz, less than 24ns)
WRITE Recovery Time
t_WR
Two or less cycle
(in case of SDCKOUT frequency 81 MHz, less than 24ns)
Data in – Command Interval
t_DAL
Four or less cycle
(in case of SDCKOUT frequency 81 MHz, less than 49ns)
Active – Pre-charge Command Interval
t_RAS
Five or less cycle
(in case of SDCKOUT frequency 81 MHz, less than 61ns)
Active – Read / Write Command Delay
Time
t_RCD
Two or less cycle
(in case of SDCKOUT frequency 81 MHz, less than 24ns)
Mode Register Set Cycle Time
t_RSC
Four or less cycle
(in case of SDCKOUT frequency 81 MHz, less than 49ns)
Note 1)
Note 2)
Note 3)
Note 4)
Note 5)
PLL must be in stable state.
Fulfill a condition Æ f_SDCK
ʾ
f_GCK1O × 2
Fulfill a condition Æ t_cSDCK × 2 ʽ t_cGCK1O
Conditions of SDRAM to be chosen.
Although some SDRAM makers may have divided and specified the interval from the auto-refresh to the
following command (t_RRC), it is necessary to be lower than t_RC.
-20-