YGV628B Datasheet, PDF (18/26 Pages) YAMAHA CORPORATION – AVDP7 Advanced Video Display Processor 7

YGV628B






● CPU Interface (Measurement Condition : CL=20pF)
No.
Item
1 A23-1 : setup time
2 A23-1 : hold time
3 CS_N: setup time
4 CS_N: hold time
5 D15-0 : output data turn on time
6 D15-0 : output data turn off time
7 D15-0 : output data valid delay time
8 D15-0 : output data hold time
9 WAIT_N, READY_N: turn on time
10 WAIT_N, READY_N: valid delay time
11 WAIT_N,READY_N: turn off time
12 D15-0 : input data setup time
13 D15-0 : input data hold time
14 WRx_N: hold time
15
READY_N: hold time
from WRx_N, RD_N inactive
Symbol
Min
Typ Max Unit Note
tsA
1
1
thA
0
1
tsCS
1
2
thCS
0
2
tonD
0
toffD
10
tdD
0
thD
0
ns
tonWAIT
0
tdWAIT
15
toffWAIT
15
tsD
tcMCLK+10
3
thD
0
3
thWR
0
thREADY
0
12
Note 1) This is a regulation for WRH_N, WRL_N, and RD_N signals. However, in case of CS_N control, it is a rule
for CS_N.
Note 2) They are the conditions of being WRH_N, WRL_N, and RD_N control. It becomes CS_N control when not
filling this regulation.
Note 3) D15-8 is the regulation to WRH_N. D7-0 is the regulation to WRL_N.
● CPU READ Cycle
A23-1
CS _N
RD_N
D15-0
WAIT _N
1
3
Hi gh-z
Hi gh-z
5
10
9
9
READY_N High-z
2
4
6
8
High-z
7
11
High-z
7
15 11
High-z
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