YGV628B Datasheet, PDF (14/26 Pages) YAMAHA CORPORATION – AVDP7 Advanced Video Display Processor 7

YGV628B






- This signal is low active.
● VSIN_N (Input Pin No.169)
- It is a vertical synchronized signal input pin.
- The external vertical synchronized signal for resetting an internal vertical counter is input.
- When not used, please make the pull-up outside of the device if necessary because this pin does not
internally have a pull-up resistor.
- This signal is low active.
● BLANK_N (Output Pin No.131)
- It is a display timing output pin.
- The signal which shows a no-display period is output.
- This signal is low active.
● YS_N (Output Pin No.130)
- It is YS signal output pin.
- YS signal at the time of superimpose is output.
- This signal is low active.
● GCK1OUT (Output Pin No.144)
● GCK2OUT (Output Pin No.107)
- It is a dot clock output pin.
- A dot clock is output.
6) System Reset
● RESET_N (Schmitt trigger type input Pin No.31)
- It is a reset pin.
- Please input a power-on reset signal.
- The reset signal input having predetermined period is surely required at the power-on.
- Since this pin does not internally have a pull-up resistor, please make the pull-up outside of the device if
necessary.
- This signal is low active. This pin uses the schmitt trigger type buffer.
7) LSI Test
● TEST2-0_N (Input Pin No. 139, 140, 141)
- It is a test mode setting pin for a device test.
- Since these pins do not internally have a pull-up resistor, please make the pull-up outside of the device.
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