YGV628B Datasheet, PDF (22/26 Pages) YAMAHA CORPORATION – AVDP7 Advanced Video Display Processor 7

YGV628B






● Display Timing Signals (Measurement Condition : CL=20pF)
No.
Item
1 ^{GCK1IN, GCK2IN : frequency}
GCK1IN, GCK2IN : cycle time
2 GCK1IN, GCK2IN : clock high level width
3 GCK1IN, GCK2IN : clock low level width
4
HSIN_N, VSIN_N, DRI5-0, DGI5-0, DBI5-0: input
data setup time
5
HSIN_N,VSIN_N,DRI5-0, DGI5-0, DBI5-0: input
data hold time
6 ^{GCK1OUT: delay time}
GCK2OUT: delay time
GCK1OUT : frequency
7
GCK1OUT : cycle time
GCK2OUT : frequency
GCK2OUT : cycle time
8 GCK1OUT, GCK2OUT : clock duty
9
YS_N, CSYNC_N, VSYNC_N, BLANK_N,
DRO5-0, DGO5-0, DBO5-0: output delay time
10
YS_N, CSYNC_N, VSYNC_N, BLANK_N,
DRO5-0, DGO5-0,DBO5-0: output hold time
Note 1) Fulfill a condition Æ fSDCK ʾ fGCK1O×2
Note 2) Fulfill a condition Æ tcSDCK×2 ʽ tcGCK1O
Note 3) In the cases of other than Analog synchronization
Symbol
f_GCKI
t_cGCKI
t_whGCKI
t_wlGCKI
t_sDI
t_hDI
t_dGCK1O
t_dGCK2O
f_GCK1O
t_cGCK1O
f_GCK2O
t_cGCK2O
t_duGCKO
t_dDISP1
t_hDISP1
Min
5
25
8
8
3
1
0
0
5
25
5
25
45
0
Typ Max Unit Note
40 MHz 1
200 ns
2
ns
ns
ns
ns
20 ns
20 ns
40 MHz
200 ns
40 MHz
200 ns
55
%
3
9
ns
ns
GCK1IN OR GCK2IN
Inputs
GCK1OUT OR GCK2OUT
Outputs
2
3
1
4
5
6
6
6
8
8
7
9
10
ˌ InputsɿHSIN_N, VSIN_N, DRI5-0, DGI5-0, DBI5-0
OutputsɿYS_N, CSYNC_N, VSYNC_N, BLANK_N, DRO5-0, DGO5-0, DBO5-0
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