YGV638 Datasheet, PDF (21/26 Pages) YAMAHA CORPORATION – a pattern graphic controller with an on-chip VRAM and the ample drawing performance enables high-resolution animated GUIs on WVGA display panels.

■ Electrical Characteristics
YGV638
· Pattern Memory Interface
No.
Items
Symbol
Min.
Typ.
Max.
Unit Note
1 MA25-1: output delay time
t_dMA
2 MOE_N: output delay time
t_dOE
2
3 MWE_N: output delay time
t_dWE
2
4 MD31-0: input setup time
t_sMD
4
5 MD31-0: input hold time
t_hMD
0
6 MD31-0: output delay time
t_dMD
7 MA25-1: output hold time from MOE_N
t_hMAR
0
MD31-0:
8
input hold time from MOE_N and MA25-1 ^thMDI
0
14
1
14
1
14
1
1
1
24
1
ns
9 MA25-1: output hold time from MWE_N
t_hMAW
0
10 MD31-0: output hold time from MWE_N
t_hMDO
1
11 MD31-0: turn off time from MWE_N
t_offMDO
1
10
12 output turn off / on time from RAHZ_N
t_on/offRA
25
Note 1) Specified value for an internal clock (SYCLK)
● Memory Access Cycle (Random Read Cycle)
SYCLK
t_dMA
MA25-1
tdOE
MOE_N
MWE_N
MD31-0
t_dMA
thMAR
t_dOE
t_sMD
t_hMDI
t_hMD
t_dWD
Note) After the read access, values of MA[25:0] and MOE_N are held until the next access to the pattern memory.
● Memory Access Cycle (Write Cycle)
SYCLK
t_dMA
t_dMA
MA25-1
tdOE
MOE_N
t_dWE
t_dMAW
t_dWE
MWE_N
MD31-0
t_dMD
t_offMDO
t_hMDO
Note) After the write access, values of MA25–1 and MOE_N are held until the next access to the pattern memory.
4GV638A21
21