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YGV638 Datasheet, PDF (18/26 Pages) YAMAHA CORPORATION – a pattern graphic controller with an on-chip VRAM and the ample drawing performance enables high-resolution animated GUIs on WVGA display panels.
■ Electrical Characteristics
YGV638
VDD33
AVDD33
VDD18
AVDD18
PLLVDD
APLLVDD
RESET_N
CS_N
XIN
tVRISE
3.0V
1.65V
tVSKWR
tVRISE
1.7V
tsR ES
VDD33 3.0V
AVDD33
VDD18
AVDD18 1.7V
PLLVDD
APLLVDD
tVSKWF
tVSKWF
3.0V
twRES
twRES
twAW
twRES
twAW
· CPU Interface
i) Parallel Interface
No.
Items
Symbol
Min.
Typ.
Max.
Unit Note
1 PS2-0: setup time
tsA
4
1
2 PS2-0: hold time
thA
0
1
3 CS_N: setup time
tsCS
0
2
4 CS_N: hold time
thCS
0
2
5 D7-0: output data turn on time
tonD
0
6 D7-0: output data turn off time
toffD
30
7 D7-0: output data valid delay time
tdD
0
8 D7-0: output data hold time
thD
0
9 WAIT_N, READY_N: turn on time
10 WAIT_N: valid delay time
tonWAIT
0
tdWAIT
ns
25
11 WAIT_N, READY_N: turn off time
toffWAIT
30
12 D7-0: input data setup time
tsD
tcSY +15
13 D7-0: input data hold time
thD
0
14 WR_N: hold time
thWR
0
15 READY_N: hold time
thREADY
0
30
16 command pulse active time
taCMD
2 × tcSY
3
17 command pulse inhibit time
tiCMD
4 × tcSY
3
18 command cycle time
tcCMD
6 × tcSY
3
Note 1) Specified values for WR_N and RD_N signals; however, in CS_N control, there are specified values for CS_N.
Note 2) Conditions that prove to be WR_N and RD_N controls. If these specified values are not met, these are for CS_N
control.
Note 3) “command pulse” means a low active pulse obtained by performing OR operation between CS_N signal and each
of WR_N and RD_N signals.
4GV638A21
18