DS897 Datasheet, PDF (9/10 Pages) Xilinx, Inc – Zynq-7000 All Programmable SoC Bus Functional Model v2.0

Zynq-7000 All Programmable SoC Bus Functional Model v2.0
Configuration Options
Table 2 shows the configuration options that are passed to the BFM through Verilog parameters.
Table 2: Configuration Options Using Verilog Parameters
BFM Parameter
Default Value
C_FCLK_CLK0_FREQ
50
C_FCLK_CLK1_FREQ
50
C_FCLK_CLK2_FREQ
50
C_FCLK_CLK3_FREQ
50
C_HIGH_OCM_EN
0
C_USE_S_AXI_HP0
0
C_USE_S_AXI_HP1
0
C_USE_S_AXI_HP2
0
C_USE_S_AXI_HP3
0
C_S_AXI_HP0_DATA_WIDTH
32
C_S_AXI_HP1_DATA_WIDTH
32
C_S_AXI_HP2_DATA_WIDTH
32
C_S_AXI_HP3_DATA_WIDTH
32
C_USE_M_AXI_GP0
0
C_USE_M_AXI_GP1
0
C_M_AXI_GP0_THREAD_ID_WIDTH
12
C_M_AXI_GP1_THREAD_ID_WIDTH
12
C_M_AXI_GP0_ENABLE_STATIC_REMAP
0
C_M_AXI_GP1_ENABLE_STATIC_REMAP
0
C_USE_S_AXI_GP0
0
C_USE_S_AXI_GP1
0
C_USE_S_AXI_ACP
0
Description
PL Clock Frequency in MHz for FCLK0.
PL Clock Frequency in MHz for FCLK1.
PL Clock Frequency in MHz for FCLK2.
PL Clock Frequency in MHz for FCLK3.
When set to '1', enables the high address range for
OCM.
When set to '1', enables the S_AXI_HP0 Slave port.
When set to '1', enables the S_AXI_HP1 Slave port.
When set to '1', enables the S_AXI_HP2 Slave port.
When set to '1', enables the S_AXI_HP3 Slave port.
Set the data-width for S_AXI_HP0 port.
Set the data-width for S_AXI_HP1 port.
Set the data-width for S_AXI_HP2 port.
Set the data-width for S_AXI_HP3 port.
When set to '1', enables the M_AXI_GP0 Master port.
When set to '1', enables the M_AXI_GP1 Master port.
Possible values are 6 and 12. This gets set to '6' with
Static remap enabled.
Possible values are 6 and 12. This gets set to '6' with
Static remap enabled.
When set to '1', enables the M_AXI_GP0 Static
remap.
When set to '1', enables the M_AXI_GP1 Static
remap.
When set to '1', enables the S_AXI_GP0 Slave port.
When set to '1', enables the S_AXI_GP1 Slave port.
When set to '1', enables the S_AXI_ACP Slave port.
Example Design
An example design and test bench named “zynq_bfm_example” is attached with AR 55345.
http://www.xilinx.com/support/answers/55345.htm
Answer Records
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Answer Records for the Zynq-7000 BFM Core
DS897 April 6, 2016
Product Specification
www.xilinx.com
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