DS897 Datasheet, PDF (3/10 Pages) Xilinx, Inc – Zynq-7000 All Programmable SoC Bus Functional Model v2.0

Zynq-7000 All Programmable SoC Bus Functional Model v2.0
Figure 2 shows the detailed architecture for the BFM logic.
X-Ref Target - Figure 2
USER I/P
User APIs
BFM _logic
Cadence
BFMs
Reset_API
AXIM_API
AXI
Translator
ZYNQ_BFM
Read_Reg
APIs
Pre-load
Memory
APIs
Read IRQs
Register
Map
256KB RAM
OCM Model
Sparse Memory
Model
Clock &
Reset
TOP INTERCONNECT MODEL(ARBITER)
AXIM AXIM
AXIS AXIS
AXIS AXIS AXIS AXIS AXIS
FRST
FCLK AXI_GP
AXI_GP
AXI_HP
AXI_ACP
Programmable Logic
Figure 2: Architecture Details
Figure 3 show the Zynq-7000 BFM test bench.
X-Ref Target - Figure 3
Testbench.v
Zynq_BFM.v
CONFIGURATION
Test.v
Test Program
(API calls)
tb.zynq_bfm.set_channel_level_info()
SCRIPTS/FUNCTION/TASK APIs
BFM LOGIC
SIGNAL INTERFACE
tb.zynq_bfm.pre_load_mem()
tb.zynq_bfm.write_data()
……
……
……
X13210
Programmable Logic (PL)
X13173
Figure 3: Test Bench
DS897 April 6, 2016
Product Specification
www.xilinx.com
3
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