DS897 Datasheet, PDF (5/10 Pages) Xilinx, Inc – Zynq-7000 All Programmable SoC Bus Functional Model v2.0

Zynq-7000 All Programmable SoC Bus Functional Model v2.0
Application Programming Interfaces
The application programming interfaces (APIs) in Table 1 can be used to configure the BFM and develop a test
program. The order of inputs and outputs for a given API must be configured as shown in Table 1, with inputs
followed by outputs in the same order as described in Table 1. The APIs in Table 1 can be used only after releasing
RESET to the BFM.
Table 1: Zynq-7000 BFM APIs
APIs
set_stop_on_error
When set to value '1', Stop the simulation on error. The default
value is 1.
set_channel_level_info
When set to value '1', channel level info for each AXI BFM is
reported. The default value is 0.
set_function_level_info
When set to value '1', function level info for each AXI BFM is
reported. The default value is 1.
set_debug_level_info
When set to value '1', debug level info for Zynq-7000 BFM is
reported, else no info is reported. The default value is 1.
Inputs
LEVEL: A bit input for the info
level.
Name: M_AXI_GP0,
M_AXI_GP1, S_ AXI_GP0,
S_AXI_GP1, S_AXI_HP0,
S_AXI_HP1, S_AXI_HP2,
S_AXI_HP3, S_AXI_ACP or
ALL
LEVEL: A bit input for the info
level.
Name: M_AXI_GP0,
M_AXI_GP1, S_ AXI_GP0,
S_AXI_GP1, S_AXI_HP0,
S_AXI_HP1, S_AXI_HP2,
S_AXI_HP3, S_AXI_ACP or
ALL
LEVEL: A bit input for the info
level.
LEVEL: A bit input for the info
level.
Outputs
None
None
None
None
set_arqos
Set the ARQOS value to be used by Slave ports for first level
arbitration scheme. The AXI Slave ARQOS input port value is
enabled by default.
Name: S_ AXI_GP0,
S_AXI_GP1, S_AXI_HP0,
S_AXI_HP1, S_AXI_HP2,
S_AXI_HP3, S_AXI_ACP
[3:0] val: ARQoS value.
None
set_awqos
Set the AWQOS value to be used by Slave ports for first level
arbitration scheme. The AXI Slave AWQOS input port value is
enabled by default.
Name: S_ AXI_GP0,
S_AXI_GP1, S_AXI_HP0,
S_AXI_HP1, S_AXI_HP2,
S_AXI_HP3, S_AXI_ACP
[3:0] val: AWQoS value.
None
fpga_soft_reset
Issue/Generate soft reset for PL.
[31:0] reset_ctrl : 32-bit input
indicating the reset o/p to be
asserted for PL.
(Details same as
FPGA_RST_CTRL register
defined in PS)
None
DS897 April 6, 2016
Product Specification
www.xilinx.com
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