DS897 Datasheet, PDF (2/10 Pages) Xilinx, Inc – Zynq-7000 All Programmable SoC Bus Functional Model v2.0

Zynq-7000 All Programmable SoC Bus Functional Model v2.0
Applications
The Zynq-7000 BFM is intended to provide a simulation environment for the Zynq-7000 PS logic, typically
replacing the processing_system7 block in a design. The Zynq-7000 BFM models the following:
• Transactions originating from PS masters through the AXI BFM master API calls
• Transactions terminating through the PS slaves to models of the OCM and DDR memories through
interconnect models
• FCLK reset and clocking support
• Input interrupts to the PS from PL
• PS register map
Functional Description
Zynq-7000 BFM consists of four main layers. Figure 1 show the Zynq-7000 BFM architecture.
X-Ref Target - Figure 1

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Figure 1: Zynq-7000 BFM Architecture
• Configuration
Configuration is implemented using Verilog parameters and is used to configure the Zynq-7000 BFM. Some
configuration must be done using configuration APIs.
• Function and Task APIs
Verilog tasks and functions that help to set:
• Datapath between processing system (PS) and programmable logic (PL) in memory mapped interfaces.
• Control path between PS and PL in register interface.
• Configure the traffic profiles for each ports.
• BFM Logic
BFM logic has the PS-PL interface with supporting functionality that contains the AXI interfaces, sparse
memory implementation, and the interconnect (arbiter) model as shown in Figure 2.
• Signal Interface
The signal interface includes the typical Verilog input and output ports and associated signals.
DS897 April 6, 2016
Product Specification
www.xilinx.com
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