DS897 Datasheet, PDF (4/10 Pages) Xilinx, Inc – Zynq-7000 All Programmable SoC Bus Functional Model v2.0

Zynq-7000 All Programmable SoC Bus Functional Model v2.0
Feature Details
The Zynq-7000 BFM is enabled with the following features:
• Pin compatible and Verilog based simulation model.
• Supports all PS AXI interfaces.
• AXI 3.0 compliant.
• 32/64–bit Data-width for AXI_HP, 32-bit for AXI_GP and 64-bit for AXI_ACP.
• ID width support as per the Zynq-7000 specification.
• Support for FIXED, INCR and WRAP transaction types.
• Support for all Zynq-7000 supported burst lengths and burst sizes.
• Protocol checking, provided by the AXI BFM models.
• Read/Write request capabilities
• System Address Decode for OCM/DDR transactions.
• System Address Decode for Register Map Read transactions (only default value of the registers can be read).
• Support for static remap for AXI_GP0 and AXI_GP1.
• Configurable latency for Read/Write responses.
• First-level arbitration scheme based on the priority indicated by the AXI QoS signals.
• Datapath connectivity between any AXI master in PL and the PS memories and register map.
• Parameters to enable and configure AXI Master and Slave ports.
• APIs to set the traffic profile and latencies for different AXI Master and Slave ports.
• Support for FPGA logic clock generation.
• Soft Reset Control for the PL.
• Sparse memory model (for DDR) and Block RAM (for OCM).
• API support to pre-load the memories, read/wait for the interrupts from PL, and checks for certain data
pattern to be updated at certain memory location.
• All unused interface signals that output to the PL are tied to a valid value.
• Semantic checks on all other unused interface signals.
• An example design that demonstrates the usage of this BFM is available for reference.
Limitations
• Support for in-order transactions only.
• Exclusive Access transfers are not supported on any of the slave ports.
• Read/Write data interleaving is not supported.
• Write access to the Register Map is not supported.
Using Zynq-7000 BFM
This section details the configuration parameters and the APIs necessary for using the Zynq-7000 BFM. It also
explains how to run the sample Verilog tests.
The interface models in the Zynq-7000 BFM are based on the AXI BFM models that are delivered with Vivado, and
requires a license for use. See Licensing and Ordering Information for more information.
DS897 April 6, 2016
Product Specification
www.xilinx.com
4
Send Feedback