XA2C256 Datasheet, PDF (8/19 Pages) Xilinx, Inc – AEC-Q100 device qualification and full PPAP support

XA2C256 CoolRunner-II Automotive CPLD
R
Internal Timing Parameters (Continued)
Symbol
Parameter⁽²⁾
I/O Standard Time Adder Delays 2.5V CMOS
T_IN25
Standard input adder
T_HYS25
Hysteresis input adder
T_OUT25
Output adder
T_SLEW25
Output slew rate adder
I/O Standard Time Adder Delays 3.3V CMOS/TTL
T_IN33
Standard input adder
T_HYS33
Hysteresis input adder
T_OUT33
Output adder
T_SLEW33
Output slew rate adder
Notes:
1. 1.5 ns input pin signal rise/fall.
-7
Min.
Max.
-
0.7
-
3.0
-
1.0
-
4.0
-
0.7
-
3.0
-
1.6
-
4.0
Switching Characteristics
AC Test Circuit
-8
Min.
Max.
Units
-
0.7
ns
-
3.0
ns
-
1.0
ns
-
4.0
ns
-
0.7
ns
-
3.0
ns
-
1.6
ns
-
4.0
ns
V_CC = V_CCIO = 1.8V, T = 25^oC
5.5
5.0
4.5
4.0
3.5
3.0
1
2
4
8
16
Number of Outputs Switching
DS092_02_092302
Figure 2: Derating Curve for T_PD
Device
Under Test
V_CC
R₁
R₂
Test Point
C_L
Output Type
LVTTL33
R₁
268Ω
R₂
235Ω
C_L
35 pF
LVCMOS33
275Ω
275Ω
35 pF
LVCMOS25
188Ω
188Ω
35pF
LVCMOS18
112.5Ω 112.5Ω
35pF
LVCMOS15
150Ω
150Ω
35pF
C_L includes test fixtures and probe capacitance.
1.5 nsec maximum rise/fall times on inputs.
DS_ACT_08_14_02
Figure 3: AC Load Circuit
8
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DS555 (v1.1) May 5, 2007
Product Specification