XA2C256 Datasheet, PDF (13/19 Pages) Xilinx, Inc – AEC-Q100 device qualification and full PPAP support

R
XA2C256 CoolRunner-II Automotive CPLD
Pin Descriptions (Continued)
Function Block
13
Macro-
cell
1
VQG100
-
TQG144
75
13
2
53
76
13
3
-
77
13
4
54
-
13
5
-
78
13
6
55
79
13
7
-
-
13
8
-
-
13
9
-
-
13
10
-
-
13
11
-
-
13
12
-
80
13
13
56
81
13
14
-
82
13
15
-
-
13
16
-
-
14
1
52
74
14
2
-
71
14
3
50
70
14
4
-
69
14
5
49
-
14
6
-
68
14
7
-
-
14
8
-
-
14
9
-
-
14
10
-
-
14
11
-
-
14
12
-
-
14
13
-
66
14
14
46
64
14
15
44
-
14
16
-
61
I/O Bank
1
1
1
1
1
1
-
-
-
-
-
1
1
1
1
1
1
1
1
1
1
1
-
-
-
-
-
1
1
1
1
1
Pin Descriptions (Continued)
Function Block
15
Macro-
cell
1
VQG100
-
TQG144
-
I/O Bank
1
15
2
-
83
1
15
3
-
-
1
15
4
-
-
1
15
5
-
-
1
15
6
-
-
1
15
7
-
-
-
15
8
-
-
-
15
9
-
-
-
15
10
-
-
-
15
11
58
85
1
15
12
59
86
1
15
13
60
87
1
15
14
61
88
1
15
15
63
91
1
15
16
64
92
1
16
1
-
-
1
16
2
-
-
1
16
3
-
-
1
16
4
-
-
1
16
5
43
60
1
16
6
42
59
1
16
7
-
-
-
16
8
-
-
-
16
9
-
-
-
16
10
-
-
-
16
11
41
58
1
16
12
40
57
1
16
13
39
56
1
16
14
-
-
1
16
15
-
54
1
16
16
-
53
1
Notes:
1. GTS = global output enable, GSR = global reset/set, GCK =
global clock, CDRST = clock divide reset, DGE = DataGATE
enable.
2. GTS, GSR and GCK pins can be used for general purpose
I/O.
DS555 (v1.1) May 5, 2007
www.xilinx.com
13
Product Specification