XA2C256 Datasheet, PDF (7/19 Pages) Xilinx, Inc – AEC-Q100 device qualification and full PPAP support

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Internal Timing Parameters
Symbol
Parameter⁽²⁾
Buffer Delays
T_IN
T_DIN
T_GCK
T_GSR
T_GTS
T_OUT
T_EN
P-term Delays
Input buffer delay
Direct data register input delay
Global Clock buffer delay
Global set/reset buffer delay
Global 3-state buffer delay
Output buffer delay
Output buffer enable/disable delay
T_CT
Control term delay
T_LOGI1
Single P-term delay adder
T_LOGI2
Multiple P-term delay adder
Macrocell Delay
T_PDI
Input to output valid
T_LDI
Setup before clock (transparent latch)
T_SUI
Setup before clock
T_HI
Hold after clock
T_ECSU
Enable clock setup time
T_ECHO
Enable clock hold time
T_COI
Clock to output valid
T_AOI
Set/reset to output valid
Feedback Delays
T_F
Feedback delay
T_OEM
Macrocell to global OE delay
I/O Standard Time Adder Delays 1.5V CMOS
T_HYS15
Hysteresis input adder
T_OUT15
Output adder
T_SLEW15
Output slew rate adder
I/O Standard Time Adder Delays 1.8V CMOS
T_HYS18
T_OUT18
T_SLEW
Hysteresis input adder
Output adder
Output slew rate adder
XA2C256 CoolRunner-II Automotive CPLD
-7
Min.
Max.
-
2.6
-
3.9
-
2.7
-
3.5
-
3.0
-
2.6
-
4.0
-
1.4
-
1.1
-
0.5
-
0.7
-
2.5
1.8
-
0.0
-
1.8
-
0.0
-
-
0.7
-
1.5
-
3.0
-
2.5
-
4.0
-
1.0
-
5.0
-
3.0
-
0.0
-
4.0
-8
Min.
Max.
Units
-
2.6
ns
-
3.3
ns
-
2.7
ns
-
4.1
ns
-
3.0
ns
-
2.6
ns
-
4.0
ns
-
2.5
ns
-
1.1
ns
-
0.5
ns
-
0.7
ns
-
2.5
ns
2.4
-
ns
0.0
-
ns
1.1
-
ns
0.0
-
ns
-
0.7
ns
-
0.9
ns
-
3.0
ns
-
2.5
ns
-
4.0
ns
-
1.0
ns
-
5.0
ns
-
3.0
ns
-
0.0
ns
-
4.0
ns
DS555 (v1.1) May 5, 2007
www.xilinx.com
7
Product Specification