XA2C256 Datasheet, PDF (2/19 Pages) Xilinx, Inc – AEC-Q100 device qualification and full PPAP support

XA2C256 CoolRunner-II Automotive CPLD
R
The use of the clock divide (division by 2) and DualEDGE
flip-flop gives the resultant CoolCLOCK feature.
DataGATE is a method to selectively disable inputs of the
CPLD that are not of interest during certain points in time.
By mapping a signal to the DataGATE function, lower power
can be achieved due to reduction in signal switching.
Another feature that eases voltage translation is I/O bank-
ing. Two I/O banks are available on the CoolRunner-II Auto-
motive 256-macrocell device that permit easy interfacing to
3.3V, 2.5V, 1.8V, and 1.5V devices.
The CoolRunner-II Automotive 256-macrocell CPLD is I/O
compatible with various I/O standards (see Table 1). This
device is also 1.5V I/O compatible with the use of
Schmitt-trigger inputs.
RealDigital Design Technology
Xilinx CoolRunner-II Automotive CPLDs are fabricated on a
0.18 micron process technology which is derived from lead-
ing edge FPGA product development. CoolRunner-II Auto-
motive CPLDs employ RealDigital, a design technique that
makes use of CMOS technology in both the fabrication and
design methodology. RealDigital design technology
employs a cascade of CMOS gates to implement sum of
products instead of traditional sense amplifier methodology.
Due to this technology, Xilinx CoolRunner-II Automotive
CPLDs achieve both high-performance and low power
operation.
Supported I/O Standards
The CoolRunner-II Automotive 256-macrocell device fea-
tures LVCMOS and LVTTL I/O implementations. See
Table 1 for I/O standard voltages. The LVTTL I/O standard
is a general purpose EIA/JEDEC standard for 3.3V applica-
tions that use an LVTTL input buffer and Push-Pull output
buffer. The LVCMOS standard is used in 3.3V, 2.5V, 1.8V
applications. CoolRunner-II Automotive CPLDs are also
1.5V I/O compatible with the use of Schmitt-trigger inputs
Table 1: I/O Standards for XA2C256
IOSTANDARD Attribute Output V_CCIO
LVTTL
3.3
LVCMOS33
3.3
LVCMOS25
2.5
LVCMOS18
1.8
LVCMOS15 ⁽¹⁾
1.5
(1) LVCMOS15 requires Schmitt-trigger inputs.
Input V_CCIO
3.3
3.3
2.5
1.8
1.5
75
50
25
0
0
50
100
150
Frequency (MHz)
DS555_01_092106
Figure 1: I_CC vs Frequency
Table 2: I_CC vs Frequency (LVCMOS 1.8V T_A = 25°C)⁽¹⁾
Frequency (MHz)
0
30
50
70
100
Typical I_CC (mA)
0.021
11.68
19.40
Notes:
1. 16-bit up/down, resettable binary counter (one counter per function block).
27.01
38.18
120
45.54
150
56.32
2
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DS555 (v1.1) May 5, 2007
Product Specification