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XA2C256 Datasheet, PDF (6/19 Pages) Xilinx, Inc – AEC-Q100 device qualification and full PPAP support
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XA2C256 CoolRunner-II Automotive CPLD
R
-7
-8
Symbol
Parameter
Min. Max. Min. Max. Units
FTOGGLE(1)
FSYSTEM1(2)
FSYSTEM2(2)
FEXT1(3)
FEXT2(3)
Internal toggle rate
Maximum system frequency
Maximum system frequency
Maximum external frequency
Maximum external frequency
- 300 - 300 MHz
- 152 - 139 MHz
- 141 - 130 MHz
-
114 - 106 MHz
- 108 - 101 MHz
TPSUD
Direct input register p-term clock setup time
1.7
- 2.0 -
ns
TPSU1
P-term clock setup time (single p-term)
1.5
- 1.9 -
ns
TPSU2
P-term clock setup time (OR array)
2.0
- 2.4 -
ns
TPHD
Direct input register p-term clock hold time
1.2
- 1.8 -
ns
TPH
P-term clock hold
1.0
- 1.3 -
ns
TPCO
P-term clock to output
-
7.3
8.4 ns
TOE/TOD
Global OE to output enable/disable
-
7.0 - 7.0 ns
TPOE/TPOD
P-term OE to output enable/disable
-
8.0 - 9.1 ns
TMOE/TMOD
Macrocell driven OE to output enable/disable
-
9.9 - 9.9 ns
TPAO
P-term set/reset to output valid
-
8.1 - 8.6 ns
TAO
Global set/reset to output valid
-
7.6 - 7.6 ns
TSUEC
Register clock enable setup time
3.1
- 3.5 -
ns
THEC
Register clock enable hold time
0.0
- 0.0 -
ns
TCW
Global clock pulse width High or Low
1.6
- 1.6 -
ns
TPCW
P-term pulse width High or Low
7.5
- 7.5 -
ns
TAPRPW
Asynchronous preset/reset pulse width (High or Low)
7.5
- 7.5 -
ns
TDGSU
Set-up before DataGATE latch assertion
0.0
- 0.0 -
ns
TDGH
Hold to DataGATE latch assertion
6.0
- 6.0 -
ns
TDGR
DataGATE recovery to new data
-
9.0 - 9.3 ns
TDGW
DataGATE low pulse width
3.5
- 3.5 -
ns
TCDRSU
CDRST setup time before falling edge GCLK2
2.0
- 2.0 -
ns
TCDRH
TCONFIG(4)
Hold time CDRST after falling edge GCLK2
Configuration time
0.0
- 0.0 -
ns
-
150 - 150 μs
Notes:
1. FTOGGLE is the maximum clock frequency to which a T-Flip Flop can reliably toggle (see the CoolRunner-II Automotive CPLD
family data sheet for more information).
2. FSYSTEM1 (1/TCYCLE) is the internal operating frequency for a device fully populated with one 16-bit counter through one p-term
per macrocell while FSYSTEM2 is through the OR array.
3. FEXT1 (1/TSU1+TCO) is the maximum external frequency using one p-term while FEXT2 is through the OR array.
4. Typical configuration current during TCONFIG is approximately 7.7 mA.
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Product Specification
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