DS092 Datasheet, PDF (8/12 Pages) Xilinx, Inc – As fast as 4.0 ns pin-to-pin logic delays

XC2C64 CoolRunner-II CPLD
R
Internal Timing Parameters (Continued)
-4
Symbol
Parameter⁽¹⁾
Min.
Max.
I/O Standard Time Adder Delays 2.5V CMOS
T_IN25
Standard input adder
-
0.5
T_HYS25
Hysteresis input adder
-
1.5
T_OUT25
Output adder
-
1.5
T_SLEW25
Output slew rate adder
-
2.0
I/O Standard Time Adder Delays 3.3V CMOS/TTL
T_IN33
Standard input adder
T_HYS33
Hysteresis input adder
T_OUT33
Output adder
T_SLEW33
Output slew rate adder
Notes:
1. 1.5 ns input pin signal rise/fall.
-
0.7
-
1.0
-
1.0
-
2.0
Switching Characteristics
-5
Min.
Max.
-
0.8
-
2.5
-
2.5
-
3.0
-
1.0
-
2.0
-
2.0
-
3.0
-7
Min. Max.
Units
-
1.0
ns
-
3.0
ns
-
3.0
ns
-
4.0
ns
-
2.0
ns
-
3.0
ns
-
3.0
ns
-
4.0
ns
VCC = 1.8V, 25^oC
6.0
5.8
5.6
4.4
4.2
4.0
12
4
8
12
16
Number of Outputs Switching
DS092_09_121501
8
www.xilinx.com
DS092 (v1.2) May 13, 2002
1-800-255-7778
Advance Product Specification