DS092 Datasheet, PDF (12/12 Pages) Xilinx, Inc – As fast as 4.0 ns pin-to-pin logic delays

XC2C64 CoolRunner-II CPLD
R
I/O⁽¹⁾
1
I/O⁽¹⁾
2
I/O⁽¹⁾
3
I/O⁽¹⁾
4
VAUX
5
I/O
6
I/O
7
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
I/O
16
I/O
17
I/O
18
I/O
19
NC
20
GND
21
I/O⁽²⁾
22
I/O⁽²⁾
23
I/O
24
NC
25
VQ100
Top View
75
NC
74
I/O
73
NC
72
I/O
71
I/O
70
I/O
69
GND
68
I/O
67
I/O
66
NC
65
NC
64
I/O
63
NC
62
GND
61
I/O
60
I/O
59
NC
58
I/O
57
Vcc
56
I/O
55
I/O
54
NC
53
I/O
52
I/O
51
V_CCIO
(1) - Global Output Enable
(2) - Global Clock
(3) - Global Set/Reset
Figure 5: VQ100 Package
Revision History
The following table shows the revision history for this document.
Date
01/03/02
03/04/02
05/13/02
Version
1.0
1.1
1.2
Revision
Initial Xilinx release.
Removed A4 from the FB1, MC16, and CP56 in the Pinout tables. Updated V_OH and V_OL
for LVCMOS 2.5V, LVCMOS 1.8V, and 1.5V DC Voltage Specifications.
Removed fast Industrial speed grade. Updated 1.5 DC Voltage, V_OH parameter from I_OH =
–0.8 mA to –0.4 mA. Updated AC Electrical Characteristics and added new parameters
12
www.xilinx.com
DS092 (v1.2) May 13, 2002
1-800-255-7778
Advance Product Specification