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DS092 Datasheet, PDF (7/12 Pages) Xilinx, Inc – As fast as 4.0 ns pin-to-pin logic delays
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XC2C64 CoolRunner-II CPLD
Internal Timing Parameters
Symbol
Parameter(1)
Buffer Delays
TIN
Input buffer delay
TFIN
Fast data register input delay
TGCK
Global Clock buffer delay
TGSR
Global set/reset buffer delay
TGTS
Global 3-state buffer delay
TOUT
Output buffer delay
TEN
Output buffer enable/disable delay
P-term Delays
TCT
Control term delay
TLOGI1
Single P-term delay adder
TLOGI2
Multiple P-term delay adder
Macrocell Delay
TPDI
Input to output valid
TSUI
Setup before clock
THI
Hold after clock
TECSU
Enable clock setup time
TECHO
Enable clock hold time
TCOI
Clock to output valid
TAOI
Set/reset to output valid
TCDBL
Clock doubler delay
Feedback Delays
TF
Feedback delay
TOEM
Macrocell to global OE delay
I/O Standard Time Adder Delays 1.5V I/O
TIN15
Standard input adder
THYS15
Hysteresis input adder
TOUT15
Output adder
TSLEW15
Output slew rate adder
I/O Standard Time Adder Delays 1.8V CMOS
TIN18
THYS18
TOUT18
TSLEW
Standard input adder
Hysteresis input adder
Output adder
Output slew rate adder
-4
Min.
Max.
-
1.3
-
1.6
-
1.2
-
1.9
-
1.4
-
1.6
-
2.5
-
0.5
-
0.4
-
0.3
-
0.4
1.2
-
0
-
1.2
-
0
-
-
0.2
-
2.0
-
0
-
1.6
-
1.0
-
0.5
-
2.0
-
0.5
-
2.0
-
0
-
2.0
-
0
-
2.0
-5
Min.
Max.
-
1.7
-
2.1
-
1.6
-
2.4
-
1.9
-
1.9
-
3.0
-
0.6
-
0.5
-
0.4
-
0.5
1.4
-
0
-
1.4
-
0
-
-
0.4
-
2.2
-
0
-
2.0
-
1.3
-
0.8
-
3.0
-
0.8
-
3.0
-
0
-
3.0
-
0
-
3.0
-7
Min. Max.
Units
-
2.4
ns
-
3.0
ns
-
2.5
ns
-
3.5
ns
-
3.0
ns
-
2.8
ns
-
4.0
ns
-
0.9
ns
-
0.8
ns
-
0.8
ns
-
0.7
ns
1.8
-
ns
0
-
ns
1.8
-
ns
0
-
ns
-
0.7
ns
-
3.0
ns
-
0
ns
-
3.0
ns
-
2.0
ns
-
1.0
ns
-
4.0
ns
-
1.0
ns
-
4.0
ns
-
0
ns
-
4.0
ns
-
0
ns
-
4.0
ns
DS092 (v1.2) May 13, 2002
www.xilinx.com
7
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