DS092 Datasheet, PDF (5/12 Pages) Xilinx, Inc – As fast as 4.0 ns pin-to-pin logic delays

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XC2C64 CoolRunner-II CPLD
LVCMOS 1.8V DC Voltage Specifications
Symbol
V_CCIO
V_IH
V_IL
V_OH
Parameter
Input source voltage
High level input voltage
Low level input voltage
High level output voltage
V_OL
Low level output voltage
I_IL
I_IH
C_JTAG
C_CLK
C_IO
Input leakage current
I/O High-Z leakage
JTAG input capacitance
Global clock input capacitance
I/O capacitance
Test Conditions
I_OH = –8 mA, V_CCIO = 1.7V
I_OH = –0.1 mA, V_CCIO = 1.7V
I_OL = 8 mA, V_CCIO = 1.7V
I_OL = 0.1 mA, V_CCIO = 1.7V
V_IN = 0 or V_CCIO to 3.9V
V_IN = 0 or V_CCIO to 3.9V
f = 1 MHz
f = 1 MHz
f = 1 MHz
Min.
1.7
0.7 x V_CCIO
–0.3
V_CCIO – 0.45
V_CCIO – 0.2
-
-
–10
–10
Max.
1.9
3.9
0.2 x V_CCIO
-
-
0.45
0.2
10
10
Units
V
V
V
V
V
V
V
µA
µA
pF
pF
pF
1.5V DC Voltage Specifications⁽¹⁾
Symbol
V_CCIO
V_IH
V_IL
V_OH
Parameter
Input source voltage
High level input voltage
Low level input voltage
High level output voltage
V_OL
Low level output voltage
I_IL
Input leakage current
I_IH
I/O High-Z leakage
C_JTAG
JTAG input capacitance
C_CLK
Global clock input capacitance
C_IO
I/O capacitance
Notes:
1. Hysteresis used on 1.5V inputs.
Test Conditions
I_OH = –4 mA, V_CCIO = 1.4V
I_OH = –0.1 mA, V_CCIO = 1.4V
I_OL = 8 mA, V_CCIO = 1.4V
I_OL = 0.1 mA, V_CCIO = 1.4V
V_IN = 0 or V_CCIO to 3.9V
V_IN = 0 or V_CCIO to 3.9V
f = 1 MHz
f = 1 MHz
f = 1 MHz
Min.
1.4
0.7 x V_CCIO
–0.3
V_CCIO – 0.45
V_CCIO – 0.2
–10
–10
Max.
1.6
3.9
0.3
0.4
0.2
10
10
Units
V
V
V
V
V
V
V
µA
µA
pF
pF
pF
DS092 (v1.2) May 13, 2002
www.xilinx.com
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