XC3100A Datasheet, PDF (7/8 Pages) Xilinx, Inc – Ultra-high-speed FPGA family with six members

IOB Switching Characteristic Guidelines (continued)
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing
patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
Speed Grade
-5
-4
Description
Symbol Min Max Min Max
Propagation Delays (Input)
Pad to Direct In (I)
Pad to Registered In (q) with
latch transparent
(XC3100A)
(XC3100)
Clock (IK) to Registered In (Q)
Set-up Time (Input)
Pad to Clock (IK) set-up time
XC3100 Family
XC3120A,XC3130A
XC3142A
XC3164A
XC3190A
XC3195A
3 T_PID
T_PTG
T_PTG
4 T_IKRI
2.8
2.5
14.0
12.0
16.0
15.0
2.8
2.5
1 T_PICK 15.0
14.0
10.9
10.6
11.0
10.7
11.2
11.0
11.5
11.2
12.0
11.6
Propagation Delays (Output)
Clock (OK) to Pad
(fast)
7 T_OKPO
5.5
5.0
same
(slew-rate limited)
7 T_OKPO
14.0
12.0
Output (O) to Pad
(fast)
10 T_OPF
4.1
3.7
same
(slew-rate limited) (XC3100A) 10 T_OPS
12.1
11.0
(XC3100) 10 T_OPF
13.0
11.0
3-state to Pad begin hi-Z (fast)
9 T_TSHZ
6.9
6.2
same
(slew-rate limited)
9 T_TSHZ
6.9
6.2
3-state to Pad active and valid (fast) (XC3100A) 8 T_TSON
10.0
10.0
same
(slew-rate limited)
8 T_TSON
18.0
17.0
3-state to Pad active and valid (fast) (XC3100) 8 T_TSON
12.0
10.0
same
(slew-rate limited)
8 T_TSON
20.0
17.0
Set-up and Hold Times (Output)
Output (O) to clock (OK) set-up time,(XC3100A) 5 T_OOK 5.0
4.5
(XC3100) 5 T_OOK 6.2
5.6
Output (O) to clock (OK) hold time
6 T_OKO 0
0
Clock
Clock High time
Clock Low time
Max. flip-flop toggle rate
11 T_IOH 2.4
12 T_IOL
2.4
F_CLK 190.0
2.0
2.0
230.0
Global Reset Delays
RESET Pad to Registered In (Q),
(XC3120/XC3120A)
(XC3195/XC3195A)
RESET Pad to output pad (fast)
(slew-rate limited)
13 T_RRI
15 T_RPO
15 T_RPO
18.0
15.0
29.5
25.0
24.0
20.0
32.0
27.0
-3
Min Max
2.2
11.0
13.0
2.2
12.0
9.4
9.5
9.7
9.9
10.3
4.4
10.0
3.3
9.0
9.0
5.5
5.5
9.0
15.0
9.0
15.0
4.0
5.0
0
1.6
1.6
270.0
13.0
21.0
17.0
23.0
-2
Min Max
2.0
11.0
1.9
8.9
9.0
9.2
9.4
9.8
4.0
9.7
3.0
8.7
5.0
5.0
8.5
14.2
3.6
0
1.3
1.3
325.0
13.0
21.0
17.0
23.0
-1
Min-Max ^Units
1.8 ns
11.0 ns
ns
1.8 ns
ns
8.5
ns
8.6
ns
8.8
ns
9.0
ns
9.4
ns
3.6 ^ns
8.9 ns
2.7 ns
8.0 ns
ns
4.5 ^ns
4.5 ns
6.5 ns
11.8 ns
ns
ns
3.2
ns
ns
0
ns
1.3
1.3
325.0
ns
ns
MHz
13.0 ^ns
21.0 ^ns
17.0 ^ns
22.0 ^ns
Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). For larger capacitive loads,
see XAPP 024. Typical slew rate limited output rise/fall times are approximately four times longer.
2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the
internal pull-up resistor or alternatively configured as a driven output or driven from an external source.
3. Input pad set-up time is specified with respect to the internal clock (IK). In order to calculate system set-up time, subtract
clock delay (pad to ik) from the input pad set-up time value. Input pad holdtime with respect to the internal clock (IK) is
negative. This means that pad level changes immediately before the internal clock edge (IK) will not be recognized.
4. T_PID, T_PTG, and T_PICK are 3 ns higher for XTAL2 when the pin is configured as a user input.
2-183