XC3100A Datasheet, PDF (5/8 Pages) Xilinx, Inc – Ultra-high-speed FPGA family with six members

CLB Switching Characteristic Guidelines (continued)
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing
patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
Speed Grade
-5
-4
-3
-2
-1
Description
Symbol Min Max Min Max Min Max Min Max Min Max Units
Combinatorial Delay
Logic Variables A, B, C, D, E,
to outputs X or Y
1 T_ILO
4.1
3.3
2.7
2.2
1.75 ^ns
Sequential delay
Clock K to outputs X or Y
8 T_CKO
3.1
2.5
2.1
1.7
1.4 ns
Clock K to outputs X or Y when Q is returned
through function generators F or G
to drive X or Y
T_QLO
6.3
5.2
4.3
3.5
3.2 ns
Set-up time before clock K
Logic Variables
A, B, C, D, E
2 T_ICK 3.1
2.5
2.1
1.8
1.7
ns
Data In
DI
4 T_DICK 2.0
1.6
1.4
1.3
1.2
ns
Enable Clock
EC
6 T_ECCK 3.8
3.2
2.7
2.5
2.3
ns
Reset Direct inactive RD
1.0
1.0
1.0
1.0
1.0
ns
Hold Time after clock k
Logic Variables
Data In
Enable Clock
A, B, C, D, E
DI
EC
Clock
Clock High time
Clock Low time
Max. flip-flop toggle rate
Reset Direct (RD)
RD width
delay from RD to outputs X or Y
Global Reset, from RESET Pad,
3 T_CKI 0
0
0
0
0
ns
5 T_CKDI 1.0
1.0
0.9
0.9
0.8
ns
7 T_CKEC 1.0
0.8
0.7
0.7
0.6
ns
11 T_CH 2.4
2.0
1.6
1.3
1.3
ns
12 T_CL 2.4
2.0
1.6
1.3
1.3
ns
F_CLK 190
230
270
325
325
MHz
13 T_RPW 3.8
3.2
2.7
2.3
2.3
ns
9 T_RIO
4.4
3.7
3.1
2.7
2.4 ns
RESET width (Low)
(XC3142A)
delay from RESET pad to outputs X or Y
T_MRW 14.0
14.0
12.0
12.0
12.0
ns
T_MRQ
17.0
14.0
12.0
12.0
12.0 ns
Notes:
The CLB K to Q output delay (T_CKO, #8) of any CLB, plus the shortest possible interconnect delay, is always longer than
the Data In hold time requirement (T_CKDI, #5) of any CLB on the same die.
T_ILO, T_QLO and T_ICK are specified for 4-input functions. For 5-input functions or base FGM functions, each of these
specifications for the XC3100A family increses by 0.50 ns (-5), 0.42 ns (-4) and 0.35 ns (-3).
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