XC3100A Datasheet, PDF (4/8 Pages) Xilinx, Inc – Ultra-high-speed FPGA family with six members

XC3100, XC3100A Logic Cell Array Family
CLB Switching Characteristic Guidelines
CLB Output (X, Y)
(Combinatorial)
CLB Input (A,B,C,D,E)
CLB Clock
CLB Input
(Direct In)
CLB Input
(Enable Clock)
CLB Output
(Flip-Flop)
1 ^TILO
2 ^TICK
12 ^TCL
4 ^TDICK
6 ^T ECCK
3 ^TCKI
11 ^T CH
5 ^TCKDI
7 ^TCKEC
8 ^TCKO
CLB Input
(Reset Direct)
CLB Output
(Flip-Flop)
9 ^T RIO ^T
13 ^TRPW
Buffer (Internal) Switching Characteristic Guidelines
Speed Grade
-5
Description
Symbol Max
Global and Alternate Clock Distribution*
Either: Normal IOB input pad through clock buffer
to any CLB or IOB clock input
Or: Fast (CMOS only) input pad through clock
buffer to any CLB or IOB clock input
T_PID
6.8
T_PIDC
5.4
TBUF driving a Horizontal Long line (L.L.)*
I to L.L. while T is Low (buffer active) (XC3100)
(XC3100A)
T↓ to L.L. active and valid with single pull-up resistor
T↓ to L.L. active and valid with pair of pull-up resistors
T↑ to L.L. High with single pull-up resistor
T↑ to L.L. High with pair of pull-up resistors
T_IO
T_IO
T_ON
T_ON
T_PUS
T_PUF
4.1
3.6
5.6
7.1
15.6
12.0
BIDI
Bidirectional buffer delay
T_BIDI
1.4
* Timing is based on the XC3142A, for other devices see XACT timing calculator.
X5424
-4
-3
-2
-1
Max
Max
Max Max Units
6.5
5.6
5.2 4.8 ns
5.1
4.3
4.0 3.8 ns
3.7
3.1
ns
3.6
3.1
3.1 2.9 ns
5.0
4.2
4.2 4.0 ns
6.5
5.7
5.7 5.5 ns
13.5
11.4
11.4 10.4 ns
10.5
8.8
8.1 7.1 ^ns
1.2
1.0
0.9 0.85 ^ns
2-180