XC3000L Datasheet, PDF (7/8 Pages) Xilinx, Inc – Part of the ZERO+ family of 3.3 V FPGAs

IOB Switching Characteristic Guidelines (continued)
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing
patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
Description
Speed Grade
-8
Symbol Min Max Min Max Min Max Units
Propagation Delays (Input)
Pad to Direct In (I)
Pad to Registered In (Q) with latch transparent
Clock (IK) to Registered In (Q)
Set-up Time (Input)
Pad to Clock (IK) set-up time
Propagation Delays (Output)
Clock (OK) to Pad (fast)
same
(slew rate limited)
Output (O) to Pad (fast)
same
(slew-rate limited)
3-state to Pad begin hi-Z (fast)
same
(slew-rate limited)
3-state to Pad active and valid (fast)
same
(slew -rate limited)
Set-up and Hold Times (Output)
Output (O) to clock (OK) set-up time
Output (O) to clock (OK) hold time
Clock
Clock High time
Clock Low time
Max. flip-flop toggle rate
Global Reset Delays (based on XC3042L)
RESET Pad to Registered In (Q)
RESET Pad to output pad (fast)
(slew-rate limited)
3 T_PID
T_PTG
4 T_IKRI
5.0
24.0
6.0
1 T_PICK 22.0
7 T_OKPO
7 T_OKPO
10 T_OPF
10 T_OPS
9 T_TSHZ
9 T_TSHZ
8 T_TSON
8 T_TSON
12.0
28.0
9.0
25.0
12.0
28.0
16.0
32.0
5 T_OOK
6 T_OKO
12.0
0
11 T_IOH
12 T_IOL
F_CLK
5.0
5.0
80.0
13 T_RRI
15 T_RPO
15 T_RPO
25.0
35.0
51.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). For larger capacitive loads,
see page XAPP024. Typical slew rate limited output rise/fall times are approximately four times longer.
2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the
internal pull-up resistor or alternatively configured as a driven output or driven from an external source.
3. Input pad set-up time is specified with respect to the internal clock (IK). In order to calculate system set-up time, subtract
clock delay (pad to IK) from the input pad set-up time value. Input pad holdtime with respect to the internal clock (IK) is
negative. This means that pad level changes immediately before the internal clock edge (IK) will not be recognized.
4. The slew-limited delays for T_OKPO, T_SHZ, T_TSON, and T_RPO are guaranteed by design and not tested.
2-175