XC3000L Datasheet, PDF (4/8 Pages) Xilinx, Inc – Part of the ZERO+ family of 3.3 V FPGAs

XC3000L Logic Cell Array Family
CLB Switching Characteristic Guidelines
CLB Output (X, Y)
(Combinatorial)
CLB Input (A,B,C,D,E)
CLB Clock
CLB Input
(Direct In)
CLB Input
(Enable Clock)
1 ^TILO
2 ^TICK
12 ^TCL
4 ^TDICK
6 ^T ECCK
CLB Output
(Flip-Flop)
3 ^TCKI
11 ^T CH
5 ^TCKDI
7 ^TCKEC
8 ^TCKO
CLB Input
(Reset Direct)
13 ^TRPW
CLB Output
(Flip-Flop)
9 ^T RIO ^T
X5424
Buffer (Internal) Switching Characteristic Guidelines
Speed Grade
Description
Symbol
Global and Alternate Clock Distribution*
Either: Normal IOB input pad through clock buffer
to any CLB or IOB clock input
Or: Fast (CMOS only) input pad through clock
buffer to any CLB or IOB clock input
TBUF driving a Horizontal Longline (L.L.)*
I to L.L. while T is Low (buffer active)
T↓ to L.L. active and valid with single pull-up resistor
T↑ to L.L. High with single pull-up resistor
T_PGC
T_PGCC
T_IO
T_ON
T_PUS
BIDI
Bidirectional buffer delay
T_BIDI
-8
Max
9.0
7 .0
5 .0
12 .0
24 .0
2 .0
Units
ns
ns
ns
ns
ns
ns
* Timing is based on the XC3042L, for other devices see XACT timing calculator.
Note: The use of two pull-up resistors per Longline, available on other XC3000 devices, is not a valid design option for XC3000L
devices
2-172
.