XC3000L Datasheet, PDF (6/8 Pages) Xilinx, Inc – Part of the ZERO+ family of 3.3 V FPGAs

XC3000L Logic Cell Array Family
IOB Switching Characteristic Guidelines
I/O Block (I)
I/O Pad Input
I/O Clock (IK/OK)
I/O Block (RI)
3 ^TPID
1 ^TPICK
12 ^TIOL
RESET
I/O Block (O)
I/O Pad Output
(Direct)
I/O Pad Output
(Registered)
10 ^TOP
5 ^TOOK
11 ^TIOH
4 ^TIKRI
13 ^TRRI
6 ^TOKO
15 ^TRPO
7 ^TOKPO
I/O Pad TS
I/O Pad Output
8 ^TTSON
9 ^TTSHZ
Vcc
PROGRAM-CONTROLLED MEMORY CELLS
OUT
INVERT
3-STATE
INVERT
OUTPUT
SELECT
SLEW
RATE
PASSIVE
PULL UP
X5425
3- STATE
T
(OUTPUT ENABLE)
O
OUT
I
DIRECT IN
Q
REGISTERED IN
DQ
FLIP
FLOP
R
QD
FLIP
FLOP
or
LATCH
R
OK
IK
OUTPUT
BUFFER
I/O PAD
TTL or
CMOS
INPUT
THRESHOLD
(GLOBAL RESET)
CK1
PROGRAM
CONTROLLED
MULTIPLEXER
CK2
= PROGRAMMABLE INTERCONNECTION POINT or PIP
X3029
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