XC3000L Datasheet, PDF (5/8 Pages) Xilinx, Inc – Part of the ZERO+ family of 3.3 V FPGAs

CLB Switching Characteristic Guidelines (continued)
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing
patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
Description
Combinatorial Delay
Logic Variables A, B, C, D, E, to outputs X or Y
FG Mode
F and FGM Mode
Speed Grade
Symbol
1 T_ILO
-8
Min Max
6.7
7.5
Units
ns
ns
Sequential delay
Clock k to outputs X or Y
8 T_CKO
7.5
ns
Clock k to outputs X or Y when Q is returned
through function generators F or G to drive X or Y
FG Mode
T_QLO
14.0
ns
F and FGM Mode
14.8
ns
Set-up time before clock K
Logic Variables
A, B, C, D, E
FG MODE
F and FGM Mode
Data In
DI
Enable Clock
EC
Hold Time after clock K
Logic Variables
Data In
Enable Clock
A, B, C, D, E
DI
EC
Clock
Clock High time
Clock Low time
Max. flip-flop toggle rate
Reset Direct (RD)
RD width
delay from RD to outputs X or Y
Global Reset (RESET Pad)*
RESET width (Low)
delay from RESET pad to outputs X or Y
2 T_ICK
5.0
5.8
4 T_DICK 5.0
6 T_ECCK 5.0
3 T_CKI
0
5 T_CKDI 2.0
7 T_CKEC 2.0
11 T_CH
5.0
12 T_CL
5.0
F_CLK 80.0
13 T_RPW 7.0
9 T_RIO
7.0
T_MRW 16.0
T_MRQ
23.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
*Timing is based on the XC3042A, for other devices see XACT timing calculator.
Notes: The CLB K to Q output delay (T_CKO, #8) of any CLB, plus the shortest possible interconnect delay, is always longer than
the Data In hold time requirement (T_CKDI, #5) of any CLB on the same die.
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