XC3000L Datasheet, PDF (1/8 Pages) Xilinx, Inc – Part of the ZERO+ family of 3.3 V FPGAs

®
XC3000L Low Voltage
Logic Cell Array Family
Product Specifications
Features
• Part of the ZERO+ family of 3.3 V FPGAs
• Low supply voltage FPGA family with five device
types
– JEDEC-compliant 3.3 V version of theXC3000A
LCA Family
– Logic densities from 1,000 to 6,000 gates
– Up to 144 user-definable I/Os
• Advanced, low power 0.8 µ CMOS static memory
technology
– Very low quiescent current consumption, ≤ 20µA
– Operating power consumption 56% less than
XC3000A, 66% less than previous generation 5 V
FPGAs
• Superset of the industry-leading XC3000 family
– Identical to the basic XC3000 in structure, pinout,
design methodology, and software tools
– 100% compatible with all XC3000, XC3000A,
XC3100 and XC3100A bitstreams
– Improved routing and additional features
• Additional programmable interconnection points
(PIPs)
– Improved access to Longlines and CLB clock
enable inputs
– Most efficient XC3000-class solution to bus-oriented
designs
• XC3000L-specific features
– Guaranteed over the 3.0 to 3.6 V Vcc range
– 4 mA output sink and source current
– Error checking of the configuration bitstream
– Soft startup starts all outputs in slew-limited mode
upon power-up
– Easy migration to the XC3400 series of HardWire
mask programmed devices for high-volume
production
Device
XC3020L
XC3030L
XC3042L
XC3064L
XC3090L
CLBs
64
100
144
224
320
Array
8x8
10 x 10
12 x 12
16 x 14
16 x 20
User I/Os
Max
64
80
96
120
144
Description
The XC3000L family of FPGAs is optimized for operation
from a nominally 3.3 V supply. Aside from the electrical and
timing parameters listed in this data sheet, the XC3000L
family is in all respects identical with the XC3000A family,
and is a superset of the XC3000 family.
The operating power consumption of Xilinx FPGAs is
almost exclusively dynamic, and it changes with the square
of the supply voltage. For a given complexity and clock
speed, the XC3000L consumes, therefore, only 44% of the
power used by the equivalent XC3000A device. In accor-
dance with its use in battery-powered equipment, the
XC3000L family was designed for the lowest possible
power-down and quiescent current consumption.
In mixed supply-voltage systems, the XC3000L, fed by a
3.3 V (nominal) supply, can directly drive any device with
TTL-like input thresholds. When a 5 V device drives the
XC3000L, a current-limiting resistor (1 kΩ) or a voltage
divider is required to prevent excessive input current.
Like the XC3000A family, XC3000L offers the following
functional improvements over the popular XC3000 family:
The XC3000L family has additional interconnect resources
to drive the I-inputs of TBUFs driving horizontal Longlines.
The CLB Clock Enable input can be driven from a second
vertical Longline. These two additions result in more
efficient and faster designs when horizontal Longlines are
used for data bussing.
During configuration, the XC3000L devices check the
bitstream format for stop bits in the appropriate positions.
Any error terminates the configuration and pulls INIT Low.
When the configuration process is finished and the device
starts up in user mode, the first activation of the outputs is
automatically slew-rate limited. This feature, called Soft
Startup, avoids the potential ground bounce when all
outputs are turned on simultaneously. After start-up, the
slew rate of the individual outputs is, as in the XC3000
family, determined by the individual configuration option.
The XC3000L family is a superset of the XC3000 family.
Any bitstream used to configure an XC3000 device config-
ures an XC3000L device the same way.
Flip-Flops
256
360
480
688
928
Horizontal
Longlines
16
20
24
32
40
Configurable
Data Bits
14,779
22,176
30,784
46,064
64,160
2-169